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* New pmgen requires explicit acceptEddie Hung2019-08-301-0/+2
* Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dspEddie Hung2019-08-305-34/+281
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| * Merge branch 'master' into xc7dspDavid Shah2019-08-3010-102/+1131
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| | * indo -> intoEddie Hung2019-08-231-1/+1
| | * Fix port hanlding in pmgenClifford Wolf2019-08-231-4/+3
| | * Add pmgen slices and choicesClifford Wolf2019-08-234-28/+276
| | * Fix test_pmgen depsMiodrag Milanovic2019-08-211-1/+1
| | * Fix copy-paste typoEddie Hung2019-08-201-1/+1
* | | Fix compile errorEddie Hung2019-08-202-8/+14
* | | Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-08-2010-90/+872
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| * | Merge branch 'master' into clifford/pmgenClifford Wolf2019-08-201-3/+1
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| | * | Ignore all generated headers for pmgen passMiodrag Milanovic2019-08-181-2/+1
| * | | Merge branch 'master' of github.com:YosysHQ/yosys into clifford/pmgenClifford Wolf2019-08-193-2/+109
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| | * | Revert "Merge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_ad...Eddie Hung2019-08-123-0/+111
| * | | Refactor pmgen rollback mechanismClifford Wolf2019-08-171-32/+21
| * | | Improvements in "test_pmgen -generate"Clifford Wolf2019-08-171-3/+23
| * | | Add pmgen "fallthrough" statementClifford Wolf2019-08-172-3/+17
| * | | Add help() callEddie Hung2019-08-161-0/+1
| * | | Minor bugfix in "test_pmgen -generate"Clifford Wolf2019-08-161-1/+1
| * | | Add pmgen finish statement, return number of matchesClifford Wolf2019-08-164-82/+116
| * | | Redesign pmgen backtracking for recursive matchingClifford Wolf2019-08-162-33/+38
| * | | Add pmgen "generate" featureClifford Wolf2019-08-163-13/+208
| * | | Refactor demo_reduce into test_pmgenClifford Wolf2019-08-164-14/+83
| * | | Add doc for pmgen semioptional statement, Add pmgen changes to CHANGELOGClifford Wolf2019-08-151-0/+3
| * | | Update pmgen documentationClifford Wolf2019-08-151-4/+58
| * | | Change pmgen default rule to reject, switch peepopt behavior to acceptClifford Wolf2019-08-155-7/+5
| * | | Add demo_reduce pass to demonstrace recursive pattern matchingClifford Wolf2019-08-154-0/+187
| * | | Improvements in pmgen for recursive patternsClifford Wolf2019-08-154-26/+132
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| * | Revert "Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER"David Shah2019-08-103-111/+0
| * | Add ice40_wrapcarry pass, rename $__ICE40_FULL_ADDER -> CARRY_WRAPPEREddie Hung2019-08-073-0/+111
* | | xilinx_dsp to be sensitive to keep attributeEddie Hung2019-08-151-1/+14
* | | SimplifyEddie Hung2019-08-151-4/+2
* | | ffH -> ffFJKGEddie Hung2019-08-152-15/+15
* | | Fixes for reverting SigSpec helper functionsEddie Hung2019-08-142-10/+14
* | | Perform C -> PCIN optimisation after pattern matcherEddie Hung2019-08-132-19/+72
* | | Revert changes to RTLIL::SigSpec methodsEddie Hung2019-08-132-7/+30
* | | Rename to XilinxDspPassEddie Hung2019-08-131-3/+3
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* | Check nusers of DSP output, not whole flopEddie Hung2019-08-091-1/+1
* | Improve ice40_dsp for non-fully-32-bit addersEddie Hung2019-08-091-3/+8
* | Another filter -> ifEddie Hung2019-08-091-2/+2
* | CleanupEddie Hung2019-08-092-18/+18
* | Pack partial-product adder DSP48E1 packingEddie Hung2019-08-092-10/+79
* | Fix checkEddie Hung2019-08-091-4/+6
* | Revert "Fix typo"Eddie Hung2019-08-091-1/+1
* | Remove muxY and ffY for nowEddie Hung2019-08-082-35/+33
* | Rework ice40_dsp to map to SB_MAC16 earlier, and check before packingEddie Hung2019-08-083-39/+83
* | Only pack registers if {A,B,P}REG = 0, do not pack $dffeEddie Hung2019-08-081-3/+6
* | Disable $dffeEddie Hung2019-08-081-8/+8
* | Fix compile errorEddie Hung2019-08-071-2/+2
* | Do not SigSpec::extract() beyond boundsEddie Hung2019-08-072-8/+10
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