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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-09 14:27:08 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-09 14:27:08 -0700 |
| commit | a002eba14a9895c7330a2741a49de02faf1af06f (patch) | |
| tree | 549118e75f452ea2d79afae9490500d50b43f0ba /passes/pmgen | |
| parent | 82cbfada1bd826fad2407010ceb243ab614ae875 (diff) | |
| download | yosys-a002eba14a9895c7330a2741a49de02faf1af06f.tar.gz yosys-a002eba14a9895c7330a2741a49de02faf1af06f.tar.bz2 yosys-a002eba14a9895c7330a2741a49de02faf1af06f.zip | |
Fix check
Diffstat (limited to 'passes/pmgen')
| -rw-r--r-- | passes/pmgen/ice40_dsp.pmg | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/passes/pmgen/ice40_dsp.pmg b/passes/pmgen/ice40_dsp.pmg index c57d3f1b3..41f34b4bd 100644 --- a/passes/pmgen/ice40_dsp.pmg +++ b/passes/pmgen/ice40_dsp.pmg @@ -119,15 +119,16 @@ match addB endmatch code addAB sigCD sigO + bool CD_SIGNED = false; if (addA) { addAB = addA; sigCD = port(addAB, \B); - sigCD.extend_u0(32, param(addAB, \B_SIGNED).as_bool()); + CD_SIGNED = param(addAB, \B_SIGNED).as_bool(); } if (addB) { addAB = addB; sigCD = port(addAB, \A); - sigCD.extend_u0(32, param(addAB, \A_SIGNED).as_bool()); + CD_SIGNED = param(addAB, \A_SIGNED).as_bool(); } if (addAB) { if (mul->type == \SB_MAC16) { @@ -139,7 +140,7 @@ code addAB sigCD sigO int natural_mul_width = GetSize(sigA) + GetSize(sigB); int actual_mul_width = GetSize(sigH); - int actual_acc_width = GetSize(sigO); + int actual_acc_width = GetSize(sigCD); if ((actual_acc_width > actual_mul_width) && (natural_mul_width > actual_mul_width)) reject; @@ -147,6 +148,7 @@ code addAB sigCD sigO reject; sigO = port(addAB, \Y); + sigCD.extend_u0(32, CD_SIGNED); } endcode @@ -255,7 +257,7 @@ code clock clock_pol sigO sigCD else if (muxB) sigCD = port(muxAB, \A); else log_abort(); - sigCD.extend_u0(32, addAB && param(addAB, \A_SIGNED).as_bool() && param(addAB, \B_SIGNED).as_bool()); + sigCD.extend_u0(32, addAB && param(addAB, \A_SIGNED).as_bool() && param(addAB, \B_SIGNED).as_bool()); } } endcode |