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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-09 14:14:28 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-09 14:14:28 -0700 |
| commit | 82cbfada1bd826fad2407010ceb243ab614ae875 (patch) | |
| tree | 3cbad891a8acfe194dc7818a5c428fa4453a4592 /passes/pmgen | |
| parent | 747690a6df9e51b4065003b50b0f07042712f112 (diff) | |
| download | yosys-82cbfada1bd826fad2407010ceb243ab614ae875.tar.gz yosys-82cbfada1bd826fad2407010ceb243ab614ae875.tar.bz2 yosys-82cbfada1bd826fad2407010ceb243ab614ae875.zip | |
Revert "Fix typo"
This reverts commit e3c39cc450a0317ad7e8234bb866d55465548c9c.
Diffstat (limited to 'passes/pmgen')
| -rw-r--r-- | passes/pmgen/ice40_dsp.pmg | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/pmgen/ice40_dsp.pmg b/passes/pmgen/ice40_dsp.pmg index 1a62c7bda..c57d3f1b3 100644 --- a/passes/pmgen/ice40_dsp.pmg +++ b/passes/pmgen/ice40_dsp.pmg @@ -143,7 +143,7 @@ code addAB sigCD sigO if ((actual_acc_width > actual_mul_width) && (natural_mul_width > actual_mul_width)) reject; - if ((actual_acc_width != actual_mul_width) && (param(mul, \A_SIGNED).as_bool() != param(addAB, \B_SIGNED).as_bool())) + if ((actual_acc_width != actual_mul_width) && (param(mul, \A_SIGNED).as_bool() != param(addAB, \A_SIGNED).as_bool())) reject; sigO = port(addAB, \Y); |