iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
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*	Perform D replacement properly	Eddie Hung	2019-09-06	1	-5/+0
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*	Add support for DREG	Eddie Hung	2019-09-06	1	-2/+57
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*	Fine tune nusers when postAdd	Eddie Hung	2019-09-06	1	-3/+3
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*	Fix macc and mul tests	Eddie Hung	2019-09-06	1	-3/+17
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*	Fix enable polarity	Eddie Hung	2019-09-06	1	-12/+12
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*	Add support for pre-adder and AD register	Eddie Hung	2019-09-06	1	-3/+98
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*	Use more index patterns	Eddie Hung	2019-09-06	1	-15/+19
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*	Fix ffPmux to cope with offset	Eddie Hung	2019-09-06	1	-12/+34
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*	Simplify filter expressions	Eddie Hung	2019-09-06	1	-6/+12
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*	Fix nusers condition in ffP	Eddie Hung	2019-09-06	1	-2/+5
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*	Check adder is <= 48 bits before packing	Eddie Hung	2019-09-06	1	-4/+5
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*	Check nusers for M and P enable muxes	Eddie Hung	2019-09-06	1	-2/+17
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*	More nusers() checks for A and B enable muxes	Eddie Hung	2019-09-06	1	-14/+27
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*	Sensitive to CEB CEM CEP polarity	Eddie Hung	2019-09-05	1	-16/+19
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*	ffAmuxAB -> ffAenpol	Eddie Hung	2019-09-05	1	-4/+6
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*	Do not check signedness of post-adder (assume taken care of by DSP)	Eddie Hung	2019-09-05	1	-1/+0
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*	Use filter instead of index; support wide enable muxes	Eddie Hung	2019-09-05	1	-4/+8
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*	Do not make ff[MP]mux semioptional, use sigmap	Eddie Hung	2019-09-05	1	-3/+6
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*	Add support for CEP	Eddie Hung	2019-09-05	1	-2/+20
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*	Add support for CEB, remove check on nusers	Eddie Hung	2019-09-05	1	-8/+20
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*	Cleanup	Eddie Hung	2019-09-05	1	-5/+2
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*	Support CEA	Eddie Hung	2019-09-05	1	-3/+23
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*	Get rid of sigBset too	Eddie Hung	2019-09-04	1	-8/+10
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*	Get rid of sigAset	Eddie Hung	2019-09-04	1	-10/+14
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*	Get rid of sigPused	Eddie Hung	2019-09-04	1	-14/+13
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*	Compute sigP properly	Eddie Hung	2019-09-04	1	-1/+1
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*	Support CEM	Eddie Hung	2019-09-04	1	-5/+27
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*	Rename muxAB to postAddMux	Eddie Hung	2019-09-03	1	-33/+14
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*	Use choices for addAB, now called postAdd	Eddie Hung	2019-09-03	1	-40/+23
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*	Add support for load value into DSP48E1.P	Eddie Hung	2019-09-03	1	-29/+41
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*	Fine tune xilinx_dsp pattern matcher	Eddie Hung	2019-08-30	1	-14/+18
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*	Remove debug	Eddie Hung	2019-08-30	1	-1/+0
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*	Add support for ffM	Eddie Hung	2019-08-30	1	-3/+36
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*	New pmgen requires explicit accept	Eddie Hung	2019-08-30	1	-0/+2
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*	xilinx_dsp to be sensitive to keep attribute	Eddie Hung	2019-08-15	1	-1/+14
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*	Perform C -> PCIN optimisation after pattern matcher	Eddie Hung	2019-08-13	1	-9/+15
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*	Check nusers of DSP output, not whole flop	Eddie Hung	2019-08-09	1	-1/+1
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*	Cleanup	Eddie Hung	2019-08-09	1	-10/+10
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*	Pack partial-product adder DSP48E1 packing	Eddie Hung	2019-08-09	1	-5/+62
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*	Remove muxY and ffY for now	Eddie Hung	2019-08-08	1	-30/+28
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*	Rework ice40_dsp to map to SB_MAC16 earlier, and check before packing	Eddie Hung	2019-08-08	1	-1/+1
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*	Only pack registers if {A,B,P}REG = 0, do not pack $dffe	Eddie Hung	2019-08-08	1	-3/+6
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*	Fine tune ice40_dsp.pmg, add support for packing subsets of registers	Eddie Hung	2019-07-19	1	-10/+10
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*	Check if RHS is empty first	Eddie Hung	2019-07-18	1	-0/+2
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*	Improve pattern matcher to match subsets of $dffe? cells	Eddie Hung	2019-07-18	1	-10/+14
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*	Improve A/B reg packing	Eddie Hung	2019-07-18	1	-6/+8
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*	Fix xilinx_dsp index cast	Eddie Hung	2019-07-18	1	-2/+2
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*	Pattern matcher to check pool of bits, not exactly	Eddie Hung	2019-07-17	1	-2/+2
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*	Signed extension	Eddie Hung	2019-07-16	1	-4/+4
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*	Add support {A,B,P}REG packing	Eddie Hung	2019-07-16	1	-29/+52
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