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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-30 15:03:43 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-30 15:03:43 -0700 |
| commit | e67f049e3b1c1ed643b86b5237b31075d0f2f212 (patch) | |
| tree | a515d17897d8187a1893ebddd58552bf45e630d4 /passes/pmgen/xilinx_dsp.pmg | |
| parent | 15bab02a1b1e20b25b6ac40914e82b31a3756382 (diff) | |
| download | yosys-e67f049e3b1c1ed643b86b5237b31075d0f2f212.tar.gz yosys-e67f049e3b1c1ed643b86b5237b31075d0f2f212.tar.bz2 yosys-e67f049e3b1c1ed643b86b5237b31075d0f2f212.zip | |
Remove debug
Diffstat (limited to 'passes/pmgen/xilinx_dsp.pmg')
| -rw-r--r-- | passes/pmgen/xilinx_dsp.pmg | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/passes/pmgen/xilinx_dsp.pmg b/passes/pmgen/xilinx_dsp.pmg index 08b432b8e..a4e1bf86d 100644 --- a/passes/pmgen/xilinx_dsp.pmg +++ b/passes/pmgen/xilinx_dsp.pmg @@ -83,7 +83,6 @@ endmatch code clock sigM sigP if (ffM) { - log_warning("M FOUND!\n"); sigM = port(ffM, \Q); for (auto b : sigM) if (b.wire->get_bool_attribute(\keep)) |