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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-03 15:53:10 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-03 15:53:10 -0700 |
| commit | 2d80866dafe9e2e2edd2d49e999c1f6a35541852 (patch) | |
| tree | 5e1b5c72e0a955bc3fc72e5b831545a319b423e1 /passes/pmgen/xilinx_dsp.pmg | |
| parent | 682153de4bb1869187e567a41c22fbed23bcdfd1 (diff) | |
| download | yosys-2d80866dafe9e2e2edd2d49e999c1f6a35541852.tar.gz yosys-2d80866dafe9e2e2edd2d49e999c1f6a35541852.tar.bz2 yosys-2d80866dafe9e2e2edd2d49e999c1f6a35541852.zip | |
Add support for load value into DSP48E1.P
Diffstat (limited to 'passes/pmgen/xilinx_dsp.pmg')
| -rw-r--r-- | passes/pmgen/xilinx_dsp.pmg | 70 |
1 files changed, 41 insertions, 29 deletions
diff --git a/passes/pmgen/xilinx_dsp.pmg b/passes/pmgen/xilinx_dsp.pmg index 132b09b2b..fdc3fa5e7 100644 --- a/passes/pmgen/xilinx_dsp.pmg +++ b/passes/pmgen/xilinx_dsp.pmg @@ -3,7 +3,7 @@ pattern xilinx_dsp state <SigBit> clock state <std::set<SigBit>> sigAset sigBset state <SigSpec> sigC sigM sigMused sigP sigPused -state <Cell*> addAB +state <Cell*> addAB muxAB match dsp select dsp->type.in(\DSP48E1) @@ -172,34 +172,7 @@ match ffP optional endmatch -//// $mux cell left behind by dff2dffe -//// would prefer not to run 'opt_expr -mux_undef' -//// since that would lose information helpful for -//// efficient wide-mux inference -//match muxP -// if !sigPused.empty() && !ffP -// select muxP->type.in($mux) -// select nusers(port(muxP, \B)) == 2 -// select port(muxP, \A).is_fully_undef() -// filter param(muxP, \WIDTH).as_int() >= GetSize(sigPused) -// filter includes(port(muxP, \B).to_sigbit_set(), sigPused.to_sigbit_set()) -// optional -//endmatch -// -//match ffY -// if muxP -// select ffY->type.in($dff, $dffe) -// select nusers(port(ffY, \D)) == 2 -// // DSP48E1 does not support clock inversion -// select param(ffY, \CLK_POLARITY).as_bool() -// filter param(ffY, \WIDTH).as_int() >= GetSize(sigPused) -// filter includes(port(ffY, \D).to_sigbit_set(), port(muxP, \Y).to_sigbit_set()) -//endmatch - -code ffP clock -// if (ffY) -// ffP = ffY; - +code ffP sigP clock if (ffP) { for (auto b : port(ffP, \Q)) if (b.wire->get_bool_attribute(\keep)) @@ -211,7 +184,46 @@ code ffP clock reject; clock = c; + + sigP = port(ffP, \Q); + } +endcode + +match muxA + if addAB + select muxA->type.in($mux) + select nusers(port(muxA, \Y)) == 2 + index <SigSpec> port(muxA, \A) === sigP + index <SigSpec> port(muxA, \Y) === sigC + optional +endmatch + +match muxB + if addAB + select muxB->type.in($mux) + select nusers(port(muxB, \Y)) == 2 + index <SigSpec> port(muxB, \B) === sigP + index <SigSpec> port(muxB, \Y) === sigC + optional +endmatch + +code sigC muxAB + if (muxA) { + muxAB = muxA; + sigC = port(muxAB, \B); + } + if (muxB) { + muxAB = muxB; + sigC = port(muxAB, \A); } + if (muxAB) { + // Ensure that adder is not used + SigSpec opmodeZ = port(dsp, \OPMODE).extract(4,3); + if (!opmodeZ.is_fully_zero()) + reject; + } +endcode +code accept; endcode |