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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-04 16:59:57 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-04 16:59:57 -0700 |
| commit | 93d798272d027f15aa930766bc3f9553f448f5cf (patch) | |
| tree | a8ec7ecb383af666e5f20648041f095efbd0f118 /passes/pmgen/xilinx_dsp.pmg | |
| parent | 229e54568e12b6ec26dfae1e5bf8597fc30d27c4 (diff) | |
| download | yosys-93d798272d027f15aa930766bc3f9553f448f5cf.tar.gz yosys-93d798272d027f15aa930766bc3f9553f448f5cf.tar.bz2 yosys-93d798272d027f15aa930766bc3f9553f448f5cf.zip | |
Compute sigP properly
Diffstat (limited to 'passes/pmgen/xilinx_dsp.pmg')
| -rw-r--r-- | passes/pmgen/xilinx_dsp.pmg | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/pmgen/xilinx_dsp.pmg b/passes/pmgen/xilinx_dsp.pmg index 9b01c22ee..c45e92d6f 100644 --- a/passes/pmgen/xilinx_dsp.pmg +++ b/passes/pmgen/xilinx_dsp.pmg @@ -189,7 +189,7 @@ code ffP sigP clock clock = c; - sigP = port(ffP, \Q); + sigP.replace(port(ffP, \D), port(ffP, \Q)); } endcode |