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* opt_muxtree: Update port_off and port_idx even for constant bitsgatecat2021-06-111-17/+16
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* opt_expr: Fix mul/div/mod by POT patterns to support >= 32 bits.Marcelina Kościelnicka2021-06-091-122/+85
| | | | | The previous code, in addition to being needlessly limitted to 32 bits in the first place, also had UB for the 31th bit (doing 1 << 31).
* opt_expr: Optimize div/mod by const 1.Marcelina Kościelnicka2021-06-091-4/+4
| | | | | | | | Turns out the code for div by a power of 2 is already almost capable of optimizing this to a shift-by-0 or and-with-0, which will be further folded into nothingness; let's beef it up to handle div by 1 as well. Fixes #2820.
* Fixing old e-mail addresses and deadnamesClaire Xenia Wolf2021-06-0817-17/+17
| | | | | | | | s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi; s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi; s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi; s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi; s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
* kernel/mem: Add sub_addr helpers.Marcelina Kościelnicka2021-05-261-6/+2
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* opt_mem: Add reset/init value support.Marcelina Kościelnicka2021-05-251-0/+12
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* opt_mem_feedback: Respect write port priority.Marcelina Kościelnicka2021-05-251-0/+15
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* opt_mem_feedback: Add wide port support.Marcelina Kościelnicka2021-05-251-14/+24
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* opt_mem_feedback: Rewrite feedback path finding logic.Marcelina Kościelnicka2021-05-241-115/+130
| | | | Fixes #2766.
* opt_mem_feedback: Convert to Mem helpers.Marcelina Kościelnicka2021-05-241-49/+28
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* memory_share: Split off feedback path finding as a separate pass.Marcelina Kościelnicka2021-05-232-0/+334
| | | | | memory_share is actually three passes in a trenchcoat. Split off the one that has the least in common with the other two as a separate pass.
* opt_mem: Remove write ports with const-0 EN.Marcelina Kościelnicka2021-05-231-0/+12
| | | | Fixes #2765.
* opt_dff: Fix NOT gates wired in reverse.Marcelina Kościelnicka2021-05-041-2/+2
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* opt_clean: Remove init attribute bits together with removed DFFs.Marcelina Kościelnicka2021-03-151-0/+4
| | | | Fixes #2546.
* opt_share: Fix X and CO signal width for shifted $alu in opt_share.Marcelina Kościelnicka2021-01-141-2/+2
| | | | | | These need to be the same length as actual Y, not visible part of Y. Fixes #2538.
* Fix use-after-free in LUT opt passStefanBruens2020-12-221-2/+4
| | | | | RTLIL::Module::remove(Cell* cell) calls `delete cell`. Any subsequent accesses of `cell` then causes undefined behavior.
* opt_mem: Use Mem helpers.Marcelina Kościelnicka2020-10-211-81/+6
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* opt_clean: Better memory handling.Marcelina Kościelnicka2020-10-081-8/+45
| | | | | | | | Previously, `$memwr` and `$meminit` cells were always preserved (along with the memory itself). With this change, they are instead part of the main cell mark-and-sweep pass: a memory (and its `$meminit` and `$memwr` cells) is only preserved iff any associated `$memrd` cell needs to be preserved.
* use the new isPublic() in a few placesN. Engelhardt2020-09-141-2/+2
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* Merge pull request #2344 from YosysHQ/mwk/opt_share-fixesclairexen2020-08-201-223/+138
|\ | | | | opt_share: Refactor, fix some bugs.
| * opt_share: Refactor, fix some bugs.Marcelina Kościelnicka2020-08-171-223/+138
| | | | | | | | | | | | Fixes #2334. Fixes #2335. Fixes #2336.
* | Merge pull request #2337 from YosysHQ/mwk/clean-keep-wireclairexen2020-08-201-4/+9
|\ \ | | | | | | opt_clean: Fix module keep rules.
| * | opt_clean: Fix module keep rules.Marcelina Kościelnicka2020-08-091-4/+9
| |/ | | | | | | | | | | - wires with keep attribute now force a module to be kept - presence of $memwr and $meminit cells no longer forces a module to be kept
* / Remove now-redundant opt_rmdff pass.Marcelina Kościelnicka2020-08-072-712/+0
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* Replace opt_rmdff with opt_dff.Marcelina Kościelnicka2020-08-071-8/+16
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* opt_expr: Remove -clkinv option, make it the default.Marcelina Kościelnicka2020-07-312-14/+14
| | | | | Adds -noclkinv option just in case the old behavior was actually useful to someone.
* Add opt_dff pass.Marcelina Kościelnicka2020-07-302-0/+876
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* opt_expr: Fix handling of $_XNOR_ cells with A = B.Marcelina Kościelnicka2020-07-291-1/+1
| | | | Fixes #2311.
* pmux2shift: Refactor to use FfInitVals.Marcelina Kościelnicka2020-07-241-15/+4
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* wreduce: Refactor to use FfInitVals.Marcelina Kościelnicka2020-07-241-37/+7
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* opt_merge: Dedup one more use of FF cell type list.Marcelina Kościelnicka2020-07-151-3/+1
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* opt_expr: Fix crash on $mul optimization with more zeros removed than Y has.Marcelina Kościelnicka2020-07-051-0/+8
| | | | Fixes #2221.
* opt_merge: use the master FF type listMarcelina Kościelnicka2020-06-301-3/+1
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* Merge pull request #2168 from whitequark/assert-unused-exprsclairexen2020-06-251-1/+1
|\ | | | | Use (and ignore) the expression provided to log_assert in NDEBUG builds
| * Remove YS_ATTRIBUTE(unused) where present just for log_assert()/log_debug().whitequark2020-06-191-1/+1
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* | Add support for new FF types in some opt passes.Marcelina Kościelnicka2020-06-233-14/+53
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* Use C++11 final/override keywords.whitequark2020-06-1817-38/+38
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* Do not optimize away FFs in "prep" and Verific fron-endClaire Wolf2020-06-091-5/+12
| | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* Add flooring division operatorXiretza2020-05-284-11/+32
| | | | | | | | | | The $div and $mod cells use truncating division semantics (rounding towards 0), as defined by e.g. Verilog. Another rounding mode, flooring (rounding towards negative infinity), can be used in e.g. VHDL. The new $divfloor cell provides this flooring division. This commit also fixes the handling of $div in opt_expr, which was previously optimized as if it was $divfloor.
* Add flooring modulo operatorXiretza2020-05-284-10/+35
| | | | | | | | | | | The $div and $mod cells use truncating division semantics (rounding towards 0), as defined by e.g. Verilog. Another rounding mode, flooring (rounding towards negative infinity), can be used in e.g. VHDL. The new $modfloor cell provides this flooring modulo (also known as "remainder" in several languages, but this name is ambiguous). This commit also fixes the handling of $mod in opt_expr, which was previously optimized as if it was $modfloor.
* opt_expr: Sx to Sz; spotted by @XiretzaEddie Hung2020-05-141-1/+1
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* Merge pull request #1994 from YosysHQ/eddie/fix_bug1758Eddie Hung2020-05-141-25/+111
|\ | | | | opt_expr: improve single-bit $and/$or/$xor/$xnor cells; gate cells too
| * Fix whitespaceEddie Hung2020-05-141-1/+1
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| * opt_expr: consume_x to require/imply !keepdcEddie Hung2020-05-081-5/+6
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| * opt_expr: restore consume_x; use for coarse grained tooEddie Hung2020-05-081-6/+6
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| * opt_expr: const_xnor replacement to pad Y with 1'b1Eddie Hung2020-04-241-1/+2
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| * opt_expr: more fixes for $xor/$xnorEddie Hung2020-04-241-23/+47
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| * opt_expr: do not group by X, more fixesEddie Hung2020-04-231-18/+59
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| * opt_expr: improve single-bit $and/$or/$xor/$xnor cells; gate cells tooEddie Hung2020-04-231-10/+29
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* | opt_clean: improve warning messageEddie Hung2020-05-141-1/+1
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