diff options
| author | whitequark <whitequark@whitequark.org> | 2020-06-19 01:32:48 +0000 |
|---|---|---|
| committer | whitequark <whitequark@whitequark.org> | 2020-06-19 15:48:58 +0000 |
| commit | 118e4caa37aa437974d9ec2ac65a4c6048cf6291 (patch) | |
| tree | bbac3bc60c6c5c7fbe417292eebd9819afb9c72a /passes/opt | |
| parent | 21692c4a2e0e70d6e0d09dd0b3c93ff70f1f236e (diff) | |
| download | yosys-118e4caa37aa437974d9ec2ac65a4c6048cf6291.tar.gz yosys-118e4caa37aa437974d9ec2ac65a4c6048cf6291.tar.bz2 yosys-118e4caa37aa437974d9ec2ac65a4c6048cf6291.zip | |
Remove YS_ATTRIBUTE(unused) where present just for log_assert()/log_debug().
Diffstat (limited to 'passes/opt')
| -rw-r--r-- | passes/opt/opt_expr.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc index c16f22b38..5c224d4bb 100644 --- a/passes/opt/opt_expr.cc +++ b/passes/opt/opt_expr.cc @@ -117,7 +117,7 @@ void replace_undriven(RTLIL::Module *module, const CellTypes &ct) } void replace_cell(SigMap &assign_map, RTLIL::Module *module, RTLIL::Cell *cell, - const std::string &info YS_ATTRIBUTE(unused), IdString out_port, RTLIL::SigSpec out_val) + const std::string &info, IdString out_port, RTLIL::SigSpec out_val) { RTLIL::SigSpec Y = cell->getPort(out_port); out_val.extend_u0(Y.size(), false); |