diff options
| author | clairexen <claire@symbioticeda.com> | 2020-06-25 18:21:51 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-06-25 18:21:51 +0200 |
| commit | c7d71f436d822bbbe3cda118591ed2b33eae3a7f (patch) | |
| tree | 48833b0478eb97cdc287545c4571249e88800ce5 /passes/opt | |
| parent | 21209d632e62983d008e121c6ffcf2815d2ae4d8 (diff) | |
| parent | c8c3c7af87804a175b3dfc60dce191b03c9741fe (diff) | |
| download | yosys-c7d71f436d822bbbe3cda118591ed2b33eae3a7f.tar.gz yosys-c7d71f436d822bbbe3cda118591ed2b33eae3a7f.tar.bz2 yosys-c7d71f436d822bbbe3cda118591ed2b33eae3a7f.zip | |
Merge pull request #2168 from whitequark/assert-unused-exprs
Use (and ignore) the expression provided to log_assert in NDEBUG builds
Diffstat (limited to 'passes/opt')
| -rw-r--r-- | passes/opt/opt_expr.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc index 170afb19c..1051a59f2 100644 --- a/passes/opt/opt_expr.cc +++ b/passes/opt/opt_expr.cc @@ -117,7 +117,7 @@ void replace_undriven(RTLIL::Module *module, const CellTypes &ct) } void replace_cell(SigMap &assign_map, RTLIL::Module *module, RTLIL::Cell *cell, - const std::string &info YS_ATTRIBUTE(unused), IdString out_port, RTLIL::SigSpec out_val) + const std::string &info, IdString out_port, RTLIL::SigSpec out_val) { RTLIL::SigSpec Y = cell->getPort(out_port); out_val.extend_u0(Y.size(), false); |