diff options
| author | Marcelina Kościelnicka <mwk@0x04.net> | 2020-07-05 00:55:38 +0200 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2020-07-05 06:31:58 +0200 |
| commit | 7afcb72c98620adaace7cc9622c4d577668f9426 (patch) | |
| tree | 762818adb15f5a4a1611d5f9ff1facbcd966bca9 /passes/opt | |
| parent | b004f0901873962ba4a6fd3e12c7bc0cc1e04032 (diff) | |
| download | yosys-7afcb72c98620adaace7cc9622c4d577668f9426.tar.gz yosys-7afcb72c98620adaace7cc9622c4d577668f9426.tar.bz2 yosys-7afcb72c98620adaace7cc9622c4d577668f9426.zip | |
opt_expr: Fix crash on $mul optimization with more zeros removed than Y has.
Fixes #2221.
Diffstat (limited to 'passes/opt')
| -rw-r--r-- | passes/opt/opt_expr.cc | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc index 1051a59f2..649ad83a6 100644 --- a/passes/opt/opt_expr.cc +++ b/passes/opt/opt_expr.cc @@ -1596,6 +1596,14 @@ skip_identity: log_debug("Removing low %d A and %d B bits from cell `%s' in module `%s'.\n", a_zeros, b_zeros, cell->name.c_str(), module->name.c_str()); + if (y_zeros >= GetSize(sig_y)) { + module->connect(sig_y, RTLIL::SigSpec(0, GetSize(sig_y))); + module->remove(cell); + + did_something = true; + goto next_cell; + } + if (a_zeros) { cell->setPort(ID::A, sig_a.extract_end(a_zeros)); cell->parameters[ID::A_WIDTH] = GetSize(sig_a) - a_zeros; |