iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Fixing old e-mail addresses and deadnames	Claire Xenia Wolf	2021-06-08	1	-1/+1
*	memory_map: Improve start_offset handling.	Marcelina Kościelnicka	2021-05-31	1	-35/+31
*	memory_map: Add wide port support.	Marcelina Kościelnicka	2021-05-25	1	-16/+17
*	extract_rdff: Add initvals parameter.	Marcelina Kościelnicka	2021-05-23	1	-2/+4
*	memory_map: Use Mem helpers.	Marcelina Kościelnicka	2020-10-21	1	-138/+81
*	Use C++11 final/override keywords.	whitequark	2020-06-18	1	-2/+2
*	Merge pull request #1603 from whitequark/ice40-ram_style	whitequark	2020-04-10	1	-6/+113
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\| *	memory_map: add -attr option, to respect inference attributes.	whitequark	2020-04-03	1	-6/+113
* \|	kernel: big fat patch to use more ID::, otherwise ID()	Eddie Hung	2020-04-02	1	-58/+58
* \|	kernel: use more ID::*	Eddie Hung	2020-04-02	1	-13/+13
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*	Use State::S{0,1}	Eddie Hung	2019-08-06	1	-1/+1
*	Consistent use of 'override' for virtual methods in derived classes.	Henner Zeller	2018-07-20	1	-2/+2
*	Added "yosys -D" feature	Clifford Wolf	2016-04-21	1	-1/+1
*	Added read-enable to memory model	Clifford Wolf	2015-09-25	1	-12/+21
*	Fixed trailing whitespaces	Clifford Wolf	2015-07-02	1	-4/+4
*	Avoid parameter values with size 0 ($mem cells)	Clifford Wolf	2015-04-05	1	-1/+6
*	Various fixes for memories with offsets	Clifford Wolf	2015-02-14	1	-2/+9
*	Added $meminit support to "memory" command	Clifford Wolf	2015-02-14	1	-2/+9
*	Renamed SIZE() to GetSize() because of name collision on Win32	Clifford Wolf	2014-10-10	1	-5/+5
*	namespace Yosys	Clifford Wolf	2014-09-27	1	-0/+4
*	Improved write address decoder generation memory_map	Clifford Wolf	2014-08-30	1	-16/+28
*	Using worker class in memory_map	Clifford Wolf	2014-08-30	1	-226/+231
*	More cleanups related to RTLIL::IdString usage	Clifford Wolf	2014-08-02	1	-2/+2
*	Renamed port access function on RTLIL::Cell, added param access functions	Clifford Wolf	2014-07-31	1	-35/+35
*	Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace	Clifford Wolf	2014-07-31	1	-1/+1
*	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28	1	-1/+0
*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27	1	-1/+1
*	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27	1	-1/+1
*	Refactoring: Renamed RTLIL::Module::wires to wires_	Clifford Wolf	2014-07-27	1	-1/+1
*	Changed a lot of code to the new RTLIL::Wire constructors	Clifford Wolf	2014-07-26	1	-39/+14
*	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26	1	-37/+37
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26	1	-37/+37
*	Use only module->addCell() and module->remove() to create and delete cells	Clifford Wolf	2014-07-25	1	-33/+9
*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22	1	-4/+4
*	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22	1	-4/+4
*	Changes to "memory" pass for new $memwr/$mem WR_EN interface	Clifford Wolf	2014-07-16	1	-35/+53
*	Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)	Clifford Wolf	2014-02-03	1	-34/+37
*	Only generate write-enable $and if WE is not constant 1 in memory_map	Clifford Wolf	2014-02-02	1	-15/+18
*	Replaced RTLIL::Const::str with generic decoder method	Clifford Wolf	2013-12-04	1	-1/+1
*	Fixed bug in synthesis of memories that are never written	Clifford Wolf	2013-10-17	1	-2/+7
*	Added help messages to memory_* passes	Clifford Wolf	2013-03-01	1	-4/+15
*	initial import	Clifford Wolf	2013-01-05	1	-0/+334