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| author | Eddie Hung <eddie@fpgeh.com> | 2020-03-12 12:57:01 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-04-02 07:14:08 -0700 |
| commit | fdafb74eb77e33e9fa2b4e591804d1d02c122ff9 (patch) | |
| tree | 49cd4fc4493b1ecfcf50aabda00aee1130124fa3 /passes/memory/memory_map.cc | |
| parent | 164dd0f6b298e416bd1ef882f21a4d0b5acfd039 (diff) | |
| download | yosys-fdafb74eb77e33e9fa2b4e591804d1d02c122ff9.tar.gz yosys-fdafb74eb77e33e9fa2b4e591804d1d02c122ff9.tar.bz2 yosys-fdafb74eb77e33e9fa2b4e591804d1d02c122ff9.zip | |
kernel: use more ID::*
Diffstat (limited to 'passes/memory/memory_map.cc')
| -rw-r--r-- | passes/memory/memory_map.cc | 26 |
1 files changed, 13 insertions, 13 deletions
diff --git a/passes/memory/memory_map.cc b/passes/memory/memory_map.cc index 65bccb5ef..b17db372a 100644 --- a/passes/memory/memory_map.cc +++ b/passes/memory/memory_map.cc @@ -248,15 +248,15 @@ struct MemoryMapWorker { RTLIL::Cell *c = module->addCell(genid(cell->name, "$rdmux", i, "", j, "", k), "$mux"); c->parameters["\\WIDTH"] = cell->parameters["\\WIDTH"]; - c->setPort("\\Y", rd_signals[k]); - c->setPort("\\S", rd_addr.extract(mem_abits-j-1, 1)); + c->setPort(ID::Y, rd_signals[k]); + c->setPort(ID::S, rd_addr.extract(mem_abits-j-1, 1)); count_mux++; - c->setPort("\\A", module->addWire(genid(cell->name, "$rdmux", i, "", j, "", k, "$a"), mem_width)); - c->setPort("\\B", module->addWire(genid(cell->name, "$rdmux", i, "", j, "", k, "$b"), mem_width)); + c->setPort(ID::A, module->addWire(genid(cell->name, "$rdmux", i, "", j, "", k, "$a"), mem_width)); + c->setPort(ID::B, module->addWire(genid(cell->name, "$rdmux", i, "", j, "", k, "$b"), mem_width)); - next_rd_signals.push_back(c->getPort("\\A")); - next_rd_signals.push_back(c->getPort("\\B")); + next_rd_signals.push_back(c->getPort(ID::A)); + next_rd_signals.push_back(c->getPort(ID::B)); } next_rd_signals.swap(rd_signals); @@ -309,21 +309,21 @@ struct MemoryMapWorker c->parameters["\\A_WIDTH"] = RTLIL::Const(1); c->parameters["\\B_WIDTH"] = RTLIL::Const(1); c->parameters["\\Y_WIDTH"] = RTLIL::Const(1); - c->setPort("\\A", w); - c->setPort("\\B", wr_bit); + c->setPort(ID::A, w); + c->setPort(ID::B, wr_bit); w = module->addWire(genid(cell->name, "$wren", i, "", j, "", wr_offset, "$y")); - c->setPort("\\Y", RTLIL::SigSpec(w)); + c->setPort(ID::Y, RTLIL::SigSpec(w)); } RTLIL::Cell *c = module->addCell(genid(cell->name, "$wrmux", i, "", j, "", wr_offset), "$mux"); c->parameters["\\WIDTH"] = wr_width; - c->setPort("\\A", sig.extract(wr_offset, wr_width)); - c->setPort("\\B", wr_data.extract(wr_offset, wr_width)); - c->setPort("\\S", RTLIL::SigSpec(w)); + c->setPort(ID::A, sig.extract(wr_offset, wr_width)); + c->setPort(ID::B, wr_data.extract(wr_offset, wr_width)); + c->setPort(ID::S, RTLIL::SigSpec(w)); w = module->addWire(genid(cell->name, "$wrmux", i, "", j, "", wr_offset, "$y"), wr_width); - c->setPort("\\Y", w); + c->setPort(ID::Y, w); sig.replace(wr_offset, w); wr_offset += wr_width; |