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| author | Clifford Wolf <clifford@clifford.at> | 2015-04-05 18:04:19 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-04-05 18:04:19 +0200 |
| commit | a1c62b79d5d554be86b4b9bd53d72704b045acde (patch) | |
| tree | 5c163f9bf47b624c846ff6b1c42c955732963de7 /passes/memory/memory_map.cc | |
| parent | 95944eb69e45837516ff9c0cba54f77ab89af754 (diff) | |
| download | yosys-a1c62b79d5d554be86b4b9bd53d72704b045acde.tar.gz yosys-a1c62b79d5d554be86b4b9bd53d72704b045acde.tar.bz2 yosys-a1c62b79d5d554be86b4b9bd53d72704b045acde.zip | |
Avoid parameter values with size 0 ($mem cells)
Diffstat (limited to 'passes/memory/memory_map.cc')
| -rw-r--r-- | passes/memory/memory_map.cc | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/passes/memory/memory_map.cc b/passes/memory/memory_map.cc index 41c4a7b12..bc94e1e25 100644 --- a/passes/memory/memory_map.cc +++ b/passes/memory/memory_map.cc @@ -81,6 +81,9 @@ struct MemoryMapWorker std::set<int> static_ports; std::map<int, RTLIL::SigSpec> static_cells_map; + int wr_ports = cell->parameters["\\WR_PORTS"].as_int(); + int rd_ports = cell->parameters["\\RD_PORTS"].as_int(); + int mem_size = cell->parameters["\\SIZE"].as_int(); int mem_width = cell->parameters["\\WIDTH"].as_int(); int mem_offset = cell->parameters["\\OFFSET"].as_int(); @@ -90,7 +93,7 @@ struct MemoryMapWorker init_data.extend_u0(mem_size*mem_width, true); // delete unused memory cell - if (cell->parameters["\\RD_PORTS"].as_int() == 0 && cell->parameters["\\WR_PORTS"].as_int() == 0) { + if (wr_ports == 0 && rd_ports == 0) { module->remove(cell); return; } @@ -99,6 +102,8 @@ struct MemoryMapWorker RTLIL::SigSpec clocks = cell->getPort("\\WR_CLK"); RTLIL::Const clocks_pol = cell->parameters["\\WR_CLK_POLARITY"]; RTLIL::Const clocks_en = cell->parameters["\\WR_CLK_ENABLE"]; + clocks_pol.bits.resize(wr_ports); + clocks_en.bits.resize(wr_ports); RTLIL::SigSpec refclock; RTLIL::State refclock_pol = RTLIL::State::Sx; for (int i = 0; i < clocks.size(); i++) { |