| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Added $ff and $_FF_ cell types | Clifford Wolf | 2016-10-12 | 4 | -1/+31 |
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| * | define PATH_MAX if not defined by limits.h | Clifford Wolf | 2016-10-11 | 1 | -0/+5 |
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| * | Improvements in assertpmux | Clifford Wolf | 2016-09-07 | 2 | -0/+19 |
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| * | Removed $aconst cell type | Clifford Wolf | 2016-08-30 | 2 | -2/+1 |
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| * | Removed $predict again | Clifford Wolf | 2016-08-28 | 3 | -11/+1 |
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| * | Fixed handling of transparent bram rd ports on ROMs | Clifford Wolf | 2016-08-27 | 1 | -0/+1 |
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| * | Added glob support to all front-ends | Clifford Wolf | 2016-08-22 | 3 | -4/+38 |
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| * | Add MSYS2-compatible build. | William D. Jones | 2016-08-16 | 1 | -2/+1 |
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| * | Use _Exit(0) on win32, always use _Exit(1) in log_error() | Clifford Wolf | 2016-08-16 | 2 | -1/+6 |
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| * | Added log_const() API | Clifford Wolf | 2016-08-09 | 2 | -0/+19 |
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| * | Use /proc/self/exe on Cygwin as well. | Yury Gribov | 2016-08-08 | 1 | -1/+1 |
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| * | Added SatGen support for $anyconst | Clifford Wolf | 2016-07-27 | 1 | -0/+22 |
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| * | Removed $predict support from SatGen | Clifford Wolf | 2016-07-27 | 1 | -9/+0 |
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| * | Added $anyconst and $aconst | Clifford Wolf | 2016-07-27 | 2 | -0/+8 |
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| * | Added "read_verilog -dump_rtlil" | Clifford Wolf | 2016-07-27 | 2 | -0/+8 |
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| * | Renamed AbstractCellEdgesDatabase::add_cell() to add_edges_from_cell() | Clifford Wolf | 2016-07-25 | 2 | -2/+2 |
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| * | Improvements in CellEdgesDatabase | Clifford Wolf | 2016-07-24 | 2 | -13/+134 |
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| * | Added CellEdgesDatabase API | Clifford Wolf | 2016-07-24 | 2 | -0/+151 |
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| * | Added satgen initstate support | Clifford Wolf | 2016-07-22 | 1 | -0/+27 |
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| * | Added $initstate cell type and vlog function | Clifford Wolf | 2016-07-21 | 3 | -3/+10 |
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| * | After reading the SV spec, using non-standard predict() instead of expect() | Clifford Wolf | 2016-07-21 | 3 | -4/+4 |
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| * | Added basic support for $expect cells | Clifford Wolf | 2016-07-13 | 4 | -8/+29 |
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| * | A few modifications after pull request comments | Ruben Undheim | 2016-06-18 | 2 | -3/+2 |
| | | | | | | - Renamed Design::packages to Design::verilog_packages - No need to include ast.h in rtlil.h | ||||
| * | Added support for SystemVerilog packages with localparam definitions | Ruben Undheim | 2016-06-18 | 2 | -0/+4 |
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| * | Added $sop SAT model | Clifford Wolf | 2016-06-17 | 1 | -0/+82 |
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| * | Improved support for $sop cells | Clifford Wolf | 2016-06-17 | 2 | -4/+16 |
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| * | Added $sop cell type and "abc -sop" | Clifford Wolf | 2016-06-17 | 2 | -1/+36 |
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| * | Added missing "#define HASHLIB_H" | Clifford Wolf | 2016-05-14 | 1 | -0/+1 |
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| * | Include <cmath> in yosys.h | Clifford Wolf | 2016-05-08 | 1 | -0/+1 |
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| * | Fixes for MXE build | Clifford Wolf | 2016-05-07 | 2 | -8/+8 |
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| * | Added "yosys -D ALL" | Clifford Wolf | 2016-04-24 | 3 | -6/+22 |
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| * | Added "yosys -D" feature | Clifford Wolf | 2016-04-21 | 4 | -9/+36 |
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| * | Minor hashlib bugfix | Clifford Wolf | 2016-04-16 | 1 | -1/+1 |
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| * | Hashlib indenting fix | Clifford Wolf | 2016-04-05 | 1 | -2/+2 |
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| * | Added ScriptPass helper class for script-like passes | Clifford Wolf | 2016-03-31 | 3 | -3/+79 |
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| * | Added log_dump() support for dict<> and pool<> containers | Clifford Wolf | 2016-03-31 | 1 | -0/+26 |
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| * | We have 2016 for a while now | Clifford Wolf | 2016-03-30 | 1 | -1/+1 |
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| * | Added .vhd file extension support | Clifford Wolf | 2016-03-30 | 1 | -0/+2 |
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| * | Merge pull request #137 from ravenexp/master | Clifford Wolf | 2016-03-28 | 1 | -0/+5 |
| |\ | | | | | Embed DATDIR make variable value into yosys binary. | ||||
| | * | Embed DATDIR make variable value into yosys binary. | Sergey Kvachonok | 2016-03-26 | 1 | -0/+5 |
| | | | | | | | | | Use it as the last resort in the share/ directory location search. | ||||
| * | | fix a cut-n-paste error in the -h help | Sebastian Kuzminsky | 2016-03-26 | 1 | -2/+2 |
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| * | Use easyer-to-read unoptimized ceil_log2() | Clifford Wolf | 2016-02-15 | 1 | -18/+5 |
| | | | | | | see here for details on the optimized version: http://svn.clifford.at/handicraft/2016/esbmc/ceilog2.c | ||||
| * | Fixed more visual studio warnings | Clifford Wolf | 2016-02-14 | 1 | -5/+3 |
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| * | Fixed some visual studio warnings | Clifford Wolf | 2016-02-13 | 3 | -4/+4 |
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| * | Added "int ceil_log2(int)" function | Clifford Wolf | 2016-02-13 | 2 | -0/+26 |
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| * | Added addBufGate module method | Clifford Wolf | 2016-02-02 | 2 | -0/+3 |
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| * | SigMap performance improvement | Clifford Wolf | 2016-02-01 | 1 | -1/+7 |
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| * | hashlib mfp<> performance improvements | Clifford Wolf | 2016-02-01 | 1 | -2/+7 |
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| * | Added reserve() method to haslib classes and | Clifford Wolf | 2016-01-31 | 1 | -2/+6 |
| | | | | | calculate hashtable size based on entries capacity, not size | ||||
| * | rtlil: Improve performance of SigSpec::extract(SigSpec, SigSpec*) | Rick Altherr | 2016-01-31 | 1 | -2/+31 |
| | | | | | | | | | Converting to a pool<SigBit> is fairly expensive due to inserts somewhat frequently causing rehashing. Instead, walk through the pattern SigSpec directly on a chunk-by-chunk basis and apply it to this SigSpec's individual bits. Using chunks for the pattern minimizes the number of iterations in the outer loop. | ||||
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index : iCE40/yosys | |
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