After reading the SV spec, using non-standard predict() instead of expect()

3 files changed, 4 insertions, 4 deletions

diff --git a/kernel/celltypes.h b/kernel/celltypes.h
index 78403fcd3..c3f05de57 100644
--- a/kernel/celltypes.h
+++ b/kernel/celltypes.h
@@ -116,7 +116,7 @@ struct CellTypes
 
 		setup_type("$assert", {A, EN}, pool<RTLIL::IdString>(), true);
 		setup_type("$assume", {A, EN}, pool<RTLIL::IdString>(), true);
-		setup_type("$expect", {A, EN}, pool<RTLIL::IdString>(), true);
+		setup_type("$predict", {A, EN}, pool<RTLIL::IdString>(), true);
 		setup_type("$equiv", {A, B}, {Y}, true);
 	}
 
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 644a83a76..cf3c80604 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -1017,7 +1017,7 @@ namespace {
 				return;
 			}
 
-			if (cell->type.in("$assert", "$assume", "$expect")) {
+			if (cell->type.in("$assert", "$assume", "$predict")) {
 				port("\\A", 1);
 				port("\\EN", 1);
 				check_expected();
@@ -1798,7 +1798,7 @@ RTLIL::Cell* RTLIL::Module::addAssume(RTLIL::IdString name, RTLIL::SigSpec sig_a
 
 RTLIL::Cell* RTLIL::Module::addExpect(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en)
 {
-	RTLIL::Cell *cell = addCell(name, "$expect");
+	RTLIL::Cell *cell = addCell(name, "$predict");
 	cell->setPort("\\A", sig_a);
 	cell->setPort("\\EN", sig_en);
 	return cell;
diff --git a/kernel/satgen.h b/kernel/satgen.h
index da892c710..22b11fe26 100644
--- a/kernel/satgen.h
+++ b/kernel/satgen.h
@@ -1347,7 +1347,7 @@ struct SatGen
 			return true;
 		}
 
-		if (cell->type == "$expect")
+		if (cell->type == "$predict")
 		{
 			std::string pf = prefix + (timestep == -1 ? "" : stringf("@%d:", timestep));
 			expects_a[pf].append((*sigmap)(cell->getPort("\\A")));