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| author | Clifford Wolf <clifford@clifford.at> | 2016-07-27 15:44:11 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2016-07-27 15:44:11 +0200 |
| commit | 9540be1d45cce45d0008a4160bc4aa70ff0dfe1d (patch) | |
| tree | 5c0c44ef35f70a243fd4a3a64bce4607f7d3515f /kernel | |
| parent | 40563129872f5a2287f54cb0dbd79534b493a5d6 (diff) | |
| download | yosys-9540be1d45cce45d0008a4160bc4aa70ff0dfe1d.tar.gz yosys-9540be1d45cce45d0008a4160bc4aa70ff0dfe1d.tar.bz2 yosys-9540be1d45cce45d0008a4160bc4aa70ff0dfe1d.zip | |
Removed $predict support from SatGen
Diffstat (limited to 'kernel')
| -rw-r--r-- | kernel/satgen.h | 9 |
1 files changed, 0 insertions, 9 deletions
diff --git a/kernel/satgen.h b/kernel/satgen.h index 31b7a3e5a..fdd2ce8b1 100644 --- a/kernel/satgen.h +++ b/kernel/satgen.h @@ -69,7 +69,6 @@ struct SatGen SigPool initial_state; std::map<std::string, RTLIL::SigSpec> asserts_a, asserts_en; std::map<std::string, RTLIL::SigSpec> assumes_a, assumes_en; - std::map<std::string, RTLIL::SigSpec> predict_a, predict_en; std::map<std::string, std::map<RTLIL::SigBit, int>> imported_signals; std::map<std::pair<std::string, int>, bool> initstates; bool ignore_div_by_zero; @@ -1374,14 +1373,6 @@ struct SatGen return true; } - if (cell->type == "$predict") - { - std::string pf = prefix + (timestep == -1 ? "" : stringf("@%d:", timestep)); - predict_a[pf].append((*sigmap)(cell->getPort("\\A"))); - predict_en[pf].append((*sigmap)(cell->getPort("\\EN"))); - return true; - } - // Unsupported internal cell types: $pow $lut // .. and all sequential cells except $dff and $_DFF_[NP]_ return false; |