| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Remove auto_wire framework (smarter than the verilog standard) | Clifford Wolf | 2013-11-24 | 2 | -8/+1 |
| * | Implemented correct handling of signed module parameters | Clifford Wolf | 2013-11-24 | 2 | -2/+3 |
| * | Added more generic _TECHMAP_ wire mechanism to techmap pass | Clifford Wolf | 2013-11-23 | 1 | -0/+6 |
| * | Some driver changes/fixes | Clifford Wolf | 2013-11-22 | 1 | -5/+5 |
| * | Added more performance measurement infrastructure | Clifford Wolf | 2013-11-22 | 1 | -0/+41 |
| * | Massive performance improvement from refactoring RTLIL::SigSpec::optimize() | Clifford Wolf | 2013-11-22 | 1 | -30/+13 |
| * | Added SigBit struct and refactored RTLIL::SigSpec::extract | Clifford Wolf | 2013-11-22 | 2 | -24/+119 |
| * | Major improvements in mem2reg and added "init" sync rules | Clifford Wolf | 2013-11-21 | 1 | -1/+2 |
| * | Added -v<level> option and some minor driver cleanups | Clifford Wolf | 2013-11-17 | 3 | -5/+23 |
| * | Added information on all internal cell types to internal checker | Clifford Wolf | 2013-11-11 | 1 | -0/+340 |
| * | Call internal checker more often | Clifford Wolf | 2013-11-10 | 2 | -9/+8 |
| * | Improved user-friendliness of "sat" and "eval" expression parsing | Clifford Wolf | 2013-11-09 | 2 | -0/+15 |
| * | Added verification of SAT model to "eval -vloghammer_report" command | Clifford Wolf | 2013-11-09 | 1 | -6/+5 |
| * | More undef-propagation related fixes | Clifford Wolf | 2013-11-08 | 1 | -0/+5 |
| * | Removed debug log from const_pow() | Clifford Wolf | 2013-11-08 | 1 | -1/+0 |
| * | Fixed handling of power operator | Clifford Wolf | 2013-11-07 | 1 | -9/+41 |
| * | Fixed more extend vs. extend_u0 issues | Clifford Wolf | 2013-11-07 | 1 | -8/+17 |
| * | Renamed extend_un0() to extend_u0() and use it in genrtlil | Clifford Wolf | 2013-11-07 | 2 | -2/+2 |
| * | Fixed type of sign extension in opt_const $eq/$ne handling | Clifford Wolf | 2013-11-07 | 2 | -0/+17 |
| * | Improved undef handling in == and != for ConstEval | Clifford Wolf | 2013-11-06 | 1 | -11/+25 |
| * | Improved width extension with regard to undef propagation | Clifford Wolf | 2013-11-06 | 2 | -67/+100 |
| * | Fixed handling of undef values in POS cells in ConstEval | Clifford Wolf | 2013-11-06 | 1 | -3/+1 |
| * | Fixed handling of undef values in MUX select input in ConstEval | Clifford Wolf | 2013-11-06 | 1 | -32/+58 |
| * | Added eval -vloghammer_report mode | Clifford Wolf | 2013-11-06 | 1 | -0/+3 |
| * | Fixed sign handling in const eval of sshl and sshr | Clifford Wolf | 2013-11-05 | 1 | -2/+6 |
| * | Write yosys version to output files | Clifford Wolf | 2013-11-03 | 2 | -3/+3 |
| * | Fixed get_share_file_name() for installed yosys | Clifford Wolf | 2013-10-27 | 1 | -2/+3 |
| * | Added API and Makefile rules for share/ files | Clifford Wolf | 2013-10-27 | 2 | -0/+22 |
| * | Added design->full_selection() helper method | Clifford Wolf | 2013-10-27 | 1 | -0/+3 |
| * | Fixed handling of boolean attributes (passes) | Clifford Wolf | 2013-10-24 | 1 | -1/+1 |
| * | Fixed handling of boolean attributes (kernel) | Clifford Wolf | 2013-10-24 | 1 | -5/+17 |
| * | Changed NEW_WIRE API to return the wire, not the signal | Clifford Wolf | 2013-10-18 | 2 | -2/+2 |
| * | Added RTLIL NEW_WIRE macro | Clifford Wolf | 2013-10-18 | 2 | -0/+13 |
| * | Added $_SR_[PN][PN]_, $_DFFSR_[PN][PN][PN]_, $_DLATCH_[PN]_ | Clifford Wolf | 2013-10-18 | 1 | -0/+14 |
| * | Added $sr, $dffsr and $dlatch cell types | Clifford Wolf | 2013-10-18 | 1 | -1/+3 |
| * | Added version info to yosys command and added -V option | Clifford Wolf | 2013-08-20 | 1 | -2/+13 |
| * | Implemented same div-by-zero behavior as found in other synthesis tools | Clifford Wolf | 2013-08-15 | 1 | -5/+28 |
| * | Fixed signed div/mod in const eval (rounding and stuff) | Clifford Wolf | 2013-08-15 | 1 | -2/+8 |
| * | Added sat -ignore_div_by_zero switch | Clifford Wolf | 2013-08-15 | 1 | -1/+6 |
| * | Added eval -brute_force_equiv_checker_x mode | Clifford Wolf | 2013-08-15 | 1 | -4/+10 |
| * | Added SAT support for $div and $mod cells | Clifford Wolf | 2013-08-11 | 1 | -0/+46 |
| * | Added "clean -purge" and ";;;" support | Clifford Wolf | 2013-08-11 | 1 | -0/+2 |
| * | Added ";;" as shortcut for "; clean;" | Clifford Wolf | 2013-08-11 | 1 | -1/+4 |
| * | Added techmap -opt mode | Clifford Wolf | 2013-08-09 | 1 | -2/+5 |
| * | Some fixes to improve determinism | Clifford Wolf | 2013-08-09 | 2 | -2/+8 |
| * | Fixed SigPool::del() method | Clifford Wolf | 2013-08-06 | 1 | -1/+1 |
| * | Added proper deallocation of history buffer | Clifford Wolf | 2013-08-06 | 1 | -0/+5 |
| * | Added "design" command (-reset, -save, -load) | Clifford Wolf | 2013-07-27 | 2 | -12/+101 |
| * | Added "help -write-web-command-reference-manual" | Clifford Wolf | 2013-07-26 | 1 | -0/+52 |
| * | Added $lut cells and abc lut mapping support | Clifford Wolf | 2013-07-23 | 1 | -0/+3 |
