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| author | Clifford Wolf <clifford@clifford.at> | 2013-10-27 09:30:58 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-10-27 09:30:58 +0100 |
| commit | bd2c8ec886cc34eac22493620de74b86b7f3628d (patch) | |
| tree | 2980fa206dd23b6c8298da491595dda5020f996e /kernel | |
| parent | 90b016716b363977cf3dfc84d9502913469296ec (diff) | |
| download | yosys-bd2c8ec886cc34eac22493620de74b86b7f3628d.tar.gz yosys-bd2c8ec886cc34eac22493620de74b86b7f3628d.tar.bz2 yosys-bd2c8ec886cc34eac22493620de74b86b7f3628d.zip | |
Added design->full_selection() helper method
Diffstat (limited to 'kernel')
| -rw-r--r-- | kernel/rtlil.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 9fae954c1..6cb471b58 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -219,6 +219,9 @@ struct RTLIL::Design { bool selected_module(RTLIL::IdString mod_name) const; bool selected_whole_module(RTLIL::IdString mod_name) const; bool selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const; + bool full_selection() const { + return selection_stack.back().full_selection; + } template<typename T1> bool selected(T1 *module) const { return selected_module(module->name); } |