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* Some driver changes/fixesClifford Wolf2013-11-221-5/+5
* Added more performance measurement infrastructureClifford Wolf2013-11-221-0/+41
* Massive performance improvement from refactoring RTLIL::SigSpec::optimize()Clifford Wolf2013-11-221-30/+13
* Added SigBit struct and refactored RTLIL::SigSpec::extractClifford Wolf2013-11-222-24/+119
* Major improvements in mem2reg and added "init" sync rulesClifford Wolf2013-11-211-1/+2
* Added -v<level> option and some minor driver cleanupsClifford Wolf2013-11-173-5/+23
* Added information on all internal cell types to internal checkerClifford Wolf2013-11-111-0/+340
* Call internal checker more oftenClifford Wolf2013-11-102-9/+8
* Improved user-friendliness of "sat" and "eval" expression parsingClifford Wolf2013-11-092-0/+15
* Added verification of SAT model to "eval -vloghammer_report" commandClifford Wolf2013-11-091-6/+5
* More undef-propagation related fixesClifford Wolf2013-11-081-0/+5
* Removed debug log from const_pow()Clifford Wolf2013-11-081-1/+0
* Fixed handling of power operatorClifford Wolf2013-11-071-9/+41
* Fixed more extend vs. extend_u0 issuesClifford Wolf2013-11-071-8/+17
* Renamed extend_un0() to extend_u0() and use it in genrtlilClifford Wolf2013-11-072-2/+2
* Fixed type of sign extension in opt_const $eq/$ne handlingClifford Wolf2013-11-072-0/+17
* Improved undef handling in == and != for ConstEvalClifford Wolf2013-11-061-11/+25
* Improved width extension with regard to undef propagationClifford Wolf2013-11-062-67/+100
* Fixed handling of undef values in POS cells in ConstEvalClifford Wolf2013-11-061-3/+1
* Fixed handling of undef values in MUX select input in ConstEvalClifford Wolf2013-11-061-32/+58
* Added eval -vloghammer_report modeClifford Wolf2013-11-061-0/+3
* Fixed sign handling in const eval of sshl and sshrClifford Wolf2013-11-051-2/+6
* Write yosys version to output filesClifford Wolf2013-11-032-3/+3
* Fixed get_share_file_name() for installed yosysClifford Wolf2013-10-271-2/+3
* Added API and Makefile rules for share/ filesClifford Wolf2013-10-272-0/+22
* Added design->full_selection() helper methodClifford Wolf2013-10-271-0/+3
* Fixed handling of boolean attributes (passes)Clifford Wolf2013-10-241-1/+1
* Fixed handling of boolean attributes (kernel)Clifford Wolf2013-10-241-5/+17
* Changed NEW_WIRE API to return the wire, not the signalClifford Wolf2013-10-182-2/+2
* Added RTLIL NEW_WIRE macroClifford Wolf2013-10-182-0/+13
* Added $_SR_[PN][PN]_, $_DFFSR_[PN][PN][PN]_, $_DLATCH_[PN]_Clifford Wolf2013-10-181-0/+14
* Added $sr, $dffsr and $dlatch cell typesClifford Wolf2013-10-181-1/+3
* Added version info to yosys command and added -V optionClifford Wolf2013-08-201-2/+13
* Implemented same div-by-zero behavior as found in other synthesis toolsClifford Wolf2013-08-151-5/+28
* Fixed signed div/mod in const eval (rounding and stuff)Clifford Wolf2013-08-151-2/+8
* Added sat -ignore_div_by_zero switchClifford Wolf2013-08-151-1/+6
* Added eval -brute_force_equiv_checker_x modeClifford Wolf2013-08-151-4/+10
* Added SAT support for $div and $mod cellsClifford Wolf2013-08-111-0/+46
* Added "clean -purge" and ";;;" supportClifford Wolf2013-08-111-0/+2
* Added ";;" as shortcut for "; clean;"Clifford Wolf2013-08-111-1/+4
* Added techmap -opt modeClifford Wolf2013-08-091-2/+5
* Some fixes to improve determinismClifford Wolf2013-08-092-2/+8
* Fixed SigPool::del() methodClifford Wolf2013-08-061-1/+1
* Added proper deallocation of history bufferClifford Wolf2013-08-061-0/+5
* Added "design" command (-reset, -save, -load)Clifford Wolf2013-07-272-12/+101
* Added "help -write-web-command-reference-manual"Clifford Wolf2013-07-261-0/+52
* Added $lut cells and abc lut mapping supportClifford Wolf2013-07-231-0/+3
* Fixed shift ops with large right hand sideClifford Wolf2013-07-091-1/+1
* Added "eval" passClifford Wolf2013-06-192-0/+86
* Fixed build with clangClifford Wolf2013-06-181-41/+69