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* Merge remote-tracking branch 'origin/master' into eddie/cleanupEddie Hung2019-08-071-0/+2
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| * Add SigSpec::extract_end() convenience functionEddie Hung2019-08-061-0/+1
| * Merge remote-tracking branch 'origin/master' into eddie/wreduce_addEddie Hung2019-08-061-3/+21
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| * | Add an SigSpec::at(offset, defval) convenience methodEddie Hung2019-07-191-0/+1
* | | Fix typosEddie Hung2019-08-061-2/+2
* | | Use IdString::begins_with()Eddie Hung2019-08-061-3/+7
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* | Add $_NMUX_, add "abc -g cmos", add proper cmos cell costsClifford Wolf2019-08-061-0/+2
* | replaced std::iterator with using statementsJakob Wenzel2019-07-251-6/+6
* | made ObjectIterator extend std::iteratorJakob Wenzel2019-07-241-2/+18
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* Allow attributes on individual switch cases in RTLIL.whitequark2019-07-081-1/+1
* Undo iterator based Module::remove() for cells, as containers will notEddie Hung2019-06-271-1/+0
* Fix leak removing cells during ABC integration; also preserve attrEddie Hung2019-06-171-0/+1
* Further cleanup based on @daveshah1Eddie Hung2019-06-141-0/+6
* Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-06-121-1/+65
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| * Refactor hierarchy wand/wor handlingClifford Wolf2019-05-281-0/+1
| * Add rewrite_sigspecs2, Improve remove() wiresClifford Wolf2019-05-151-0/+60
| * Merge pull request #991 from kristofferkoch/gcc9-warningsClifford Wolf2019-05-081-0/+3
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| | * Fix all warnings that occurred when compiling with gcc9Kristoffer Ellersgaard Koch2019-05-081-0/+3
| * | Improve write_verilog specify supportClifford Wolf2019-05-041-1/+1
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* | Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-04-221-1/+26
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| * Merge pull request #905 from christian-krieg/feature/python_bindingsClifford Wolf2019-04-221-1/+26
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| | * Merge remote-tracking branch 'origin/master' into feature/python_bindingsBenedikt Tutzer2019-03-281-6/+74
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| | * | Deleted duplicate DestructorBenedikt Tutzer2018-08-211-1/+0
| | * | added some checks if python is enabled to make sure everything compiles if py...Benedikt Tutzer2018-08-201-0/+1
| | * | Added Wrappers for:Benedikt Tutzer2018-08-131-3/+11
| | * | added destructors for wires and cellsBenedikt Tutzer2018-07-101-1/+2
| | * | multiple designs can now exist independent from each other. Cells/Wires/Modul...Benedikt Tutzer2018-07-091-0/+16
* | | | Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-04-201-1/+1
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| * | | Add "wbflip" commandClifford Wolf2019-04-201-1/+1
| * | | Ignore 'whitebox' attr in flatten with "-wb" optionEddie Hung2019-04-181-2/+2
* | | | Ignore 'whitebox' attr in flatten with "-wb" optionEddie Hung2019-04-181-2/+2
* | | | Merge remote-tracking branch 'origin/clifford/whitebox' into xaigEddie Hung2019-04-181-0/+4
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| * | | Add "whitebox" attribute, add "read_verilog -wb"Clifford Wolf2019-04-181-0/+4
* | | | Merge branch 'master' into xaigEddie Hung2019-04-081-5/+68
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| * | | Add "read_ilang -lib"Clifford Wolf2019-04-051-0/+1
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| * | Add RTLIL::Const::ext[su](), fix RTLIL::SigSpec::extend_u0 for 0-size signalsClifford Wolf2019-03-231-0/+8
| * | Improve determinism of IdString DB for similar scriptsClifford Wolf2019-03-111-5/+59
* | | Add IdString::ends_with()Eddie Hung2019-02-261-0/+6
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* | proc_clean: remove any empty cases if all cases use all-def compare.whitequark2018-12-231-0/+4
* | Support for 'modports' for System Verilog interfacesRuben Undheim2018-10-121-1/+1
* | Synthesis support for SystemVerilog interfacesRuben Undheim2018-10-121-0/+2
* | Consistent use of 'override' for virtual methods in derived classes.Henner Zeller2018-07-201-1/+1
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* Add $allconst and $allseq cell typesClifford Wolf2018-02-231-0/+2
* Bugfix in hierarchy handling of blackbox module portsClifford Wolf2018-01-051-1/+1
* Add RTLIL::Const::is_fully_ones()Clifford Wolf2017-12-141-0/+1
* Add SigSpec::is_fully_ones()Clifford Wolf2017-12-141-0/+1
* Add src arguments to all cell creator helper functionsClifford Wolf2017-09-091-153/+153
* Merge remote-tracking branch 'upstream/master'Jason Lowdermilk2017-08-301-0/+4
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| * Add {get,set}_src_attribute() methods on RTLIL::AttrObjectClifford Wolf2017-08-301-0/+4
* | Add support for source line tracking through synthesis phaseJason Lowdermilk2017-08-291-18/+18
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