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| author | Ruben Undheim <ruben.undheim@gmail.com> | 2018-10-12 20:58:37 +0200 |
|---|---|---|
| committer | Ruben Undheim <ruben.undheim@gmail.com> | 2018-10-12 21:11:48 +0200 |
| commit | 458a94059e6738d93a87ddb9af282d0e1d28791d (patch) | |
| tree | 7d2e8430a312360dd5d7049850b5493eb1dc1734 /kernel/rtlil.h | |
| parent | 75009ada3c2a4bcd38c52c8fb871c9e8c1f2e6b1 (diff) | |
| download | yosys-458a94059e6738d93a87ddb9af282d0e1d28791d.tar.gz yosys-458a94059e6738d93a87ddb9af282d0e1d28791d.tar.bz2 yosys-458a94059e6738d93a87ddb9af282d0e1d28791d.zip | |
Support for 'modports' for System Verilog interfaces
Diffstat (limited to 'kernel/rtlil.h')
| -rw-r--r-- | kernel/rtlil.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 8a2b0a4f3..276540aa1 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -907,7 +907,7 @@ public: Module(); virtual ~Module(); virtual RTLIL::IdString derive(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, bool mayfail = false); - virtual RTLIL::IdString derive(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, dict<RTLIL::IdString, RTLIL::Module*> interfaces, bool mayfail = false); + virtual RTLIL::IdString derive(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, dict<RTLIL::IdString, RTLIL::Module*> interfaces, dict<RTLIL::IdString, RTLIL::IdString> modports, bool mayfail = false); virtual size_t count_id(RTLIL::IdString id); virtual void reprocess_module(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Module *> local_interfaces); |