| Commit message (Expand) | Author | Age | Files | Lines |
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| * | Simplify some RTLIL destructors | Rupert Swarbrick | 2021-06-14 | 1 | -10/+10 |
| * | opt_expr: Fix mul/div/mod by POT patterns to support >= 32 bits. | Marcelina Kościelnicka | 2021-06-09 | 1 | -0/+33 |
| * | Fixing old e-mail addresses and deadnames | Claire Xenia Wolf | 2021-06-08 | 1 | -1/+1 |
| * | kernel/rtlil: Extract some helpers for checking memory cell types. | Marcelina Kościelnicka | 2021-05-22 | 1 | -0/+10 |
| * | rtlil: add const accessors for modules, wires, and cells | Zachary Snow | 2021-03-25 | 1 | -0/+5 |
| * | blackbox: Include whiteboxed modules | gatecat | 2021-03-17 | 1 | -2/+2 |
| * | rtlil: Disallow 0-width chunks in SigSpec. | Marcelina Kościelnicka | 2021-03-15 | 1 | -18/+49 |
| * | Add support for memory writes in processes. | Marcelina Kościelnicka | 2021-03-08 | 1 | -0/+1 |
| * | Replace assert in addModule with more useful error message | Dan Ravensloft | 2021-03-06 | 1 | -1/+2 |
| * | bugpoint: add -wires option. | whitequark | 2020-12-07 | 1 | -1/+1 |
| * | Replace "ILANG" with "RTLIL" everywhere. | whitequark | 2020-08-26 | 1 | -2/+2 |
| * | Ensure \A_SIGNED is never used with $shiftx | Xiretza | 2020-08-18 | 1 | -1/+5 |
| * | Add add* functions for the new FF types | Marcelina Kościelnicka | 2020-06-23 | 1 | -0/+193 |
| * | Add new builtin FF types | Marcelina Kościelnicka | 2020-06-23 | 1 | -47/+224 |
| * | RTLIL: add Module::addProcess, use it in Module::cloneInto. NFC. | whitequark | 2020-06-09 | 1 | -2/+10 |
| * | flatten: preserve original object names via hdlname attribute. | whitequark | 2020-06-08 | 1 | -0/+16 |
| * | RTLIL: use {get,set}_string_attribute in {get,set}_strpool_attribute. | whitequark | 2020-06-08 | 1 | -2/+2 |
| * | Merge pull request #2105 from whitequark/split-flatten-off-techmap | clairexen | 2020-06-08 | 1 | -0/+12 |
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| | * | RTLIL: factor out RTLIL::Module::addMemory. NFC. | whitequark | 2020-06-04 | 1 | -0/+12 |
| * | | Merge pull request #2006 from jersey99/signed-in-rtlil-wire | whitequark | 2020-06-04 | 1 | -0/+2 |
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| | * | Preserve 'signed'-ness of a verilog wire through RTLIL | Vamsi K Vytla | 2020-04-27 | 1 | -0/+2 |
| * | | Add flooring division operator | Xiretza | 2020-05-28 | 1 | -1/+2 |
| * | | Add flooring modulo operator | Xiretza | 2020-05-28 | 1 | -1/+2 |
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| * | kernel: Cell::getParam() to throw exception again if not found | Eddie Hung | 2020-04-22 | 1 | -3/+2 |
| * | Use default parameter value in getParam | Marcelina Kościelnicka | 2020-04-21 | 1 | -1/+10 |
| * | ilang, ast: Store parameter order and default value information. | Marcelina Kościelnicka | 2020-04-21 | 1 | -1/+2 |
| * | rtlil: add AttrObject::has_attribute. | whitequark | 2020-04-16 | 1 | -0/+5 |
| * | rtlil: add AttrObject::{get,set}_string_attribute. | whitequark | 2020-04-16 | 1 | -17/+17 |
| * | Merge pull request #1927 from YosysHQ/eddie/design_remove_assert | Eddie Hung | 2020-04-16 | 1 | -0/+1 |
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| | * | kernel: Design::remove(RTLIL::Module *) to check refcount_modules_ | Eddie Hung | 2020-04-14 | 1 | -0/+1 |
| * | | kernel: Module::makeblackbox() to clear connections too | Eddie Hung | 2020-04-13 | 1 | -0/+2 |
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| * | Merge pull request #1858 from YosysHQ/eddie/fix1856 | Eddie Hung | 2020-04-09 | 1 | -1/+1 |
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| | * | kernel: include "kernel/constids.inc" instead of "constids.inc" | Eddie Hung | 2020-04-09 | 1 | -1/+1 |
| * | | [NFCI] Deduplicate builtin FF cell types list | Marcelina Kościelnicka | 2020-04-09 | 1 | -0/+47 |
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| * | kernel: big fat patch to use more ID::*, otherwise ID(*) | Eddie Hung | 2020-04-02 | 1 | -410/+410 |
| * | kernel: Use constids.inc for global/constant IdStrings | Eddie Hung | 2020-04-02 | 1 | -6/+4 |
| * | Merge pull request #1845 from YosysHQ/eddie/kernel_speedup | Eddie Hung | 2020-04-02 | 1 | -288/+244 |
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| | * | kernel: pass-by-value into Design::scratchpad_set_string() too | Eddie Hung | 2020-03-27 | 1 | -2/+2 |
| | * | kernel: Cell::set{Port,Param}() to pass by value, but use std::move | Eddie Hung | 2020-03-26 | 1 | -5/+5 |
| | * | kernel: SigSpec copies to not trigger pack() | Eddie Hung | 2020-03-18 | 1 | -33/+4 |
| | * | kernel: more pass by const ref, more speedups | Eddie Hung | 2020-03-18 | 1 | -180/+174 |
| | * | kernel: speedup | Eddie Hung | 2020-03-18 | 1 | -30/+23 |
| | * | kernel: fix DeleteWireWorker | Eddie Hung | 2020-03-17 | 1 | -9/+4 |
| | * | kernel: SigSpec use more const& + overloads to prevent implicit SigSpec | Eddie Hung | 2020-03-13 | 1 | -31/+39 |
| | * | kernel: optimise Module::remove(const pool<RTLIL::Wire*>() | Eddie Hung | 2020-03-12 | 1 | -10/+5 |
| * | | Add support for SystemVerilog-style `define to Verilog frontend | Rupert Swarbrick | 2020-03-27 | 1 | -0/+2 |
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| * | Closes #1717. Add more precise Verilog source location information to AST and... | Alberto Gonzalez | 2020-02-23 | 1 | -2/+0 |
| * | specify: system timing checks to accept min:typ:max triple | Eddie Hung | 2020-02-13 | 1 | -2/+6 |
| * | Add RTLIL::constpad, init by yosys_setup(); use for abc9 | Eddie Hung | 2020-01-08 | 1 | -0/+1 |
| * | Always create $shl, $shr, $sshl, $sshr cells with unsigned B inputs | Clifford Wolf | 2020-01-02 | 1 | -4/+25 |
