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| author | whitequark <whitequark@whitequark.org> | 2020-12-07 09:24:35 +0000 |
|---|---|---|
| committer | whitequark <whitequark@whitequark.org> | 2020-12-07 09:24:35 +0000 |
| commit | 1838edf35cbd558d3a9a9c4a1ea10e080e8d56ab (patch) | |
| tree | 650a1032eb4945e99764be94fb9841dc45ebb5e8 /kernel/rtlil.cc | |
| parent | 2b474a01e11342d7ed3e8d67b0c4561fa8628429 (diff) | |
| download | yosys-1838edf35cbd558d3a9a9c4a1ea10e080e8d56ab.tar.gz yosys-1838edf35cbd558d3a9a9c4a1ea10e080e8d56ab.tar.bz2 yosys-1838edf35cbd558d3a9a9c4a1ea10e080e8d56ab.zip | |
bugpoint: add -wires option.
Diffstat (limited to 'kernel/rtlil.cc')
| -rw-r--r-- | kernel/rtlil.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index a9f585616..1faf376e7 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1826,7 +1826,7 @@ void RTLIL::Module::remove(const pool<RTLIL::Wire*> &wires) sig.pack(); for (auto &c : sig.chunks_) if (c.wire != NULL && wires_p->count(c.wire)) { - c.wire = module->addWire(NEW_ID, c.width); + c.wire = module->addWire(stringf("$delete_wire$%d", autoidx++), c.width); c.offset = 0; } } |