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| author | Marcelina Kościelnicka <mwk@0x04.net> | 2020-04-16 15:51:03 +0200 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2020-04-21 19:09:00 +0200 |
| commit | 06a344efcb4a8c56f230715481ce07e715a7a4b3 (patch) | |
| tree | 7d5aa868e0843ab0309b7325b88f145493d962e9 /kernel/rtlil.cc | |
| parent | 79efaa65ad73520e4354bdc33622216bf29892fc (diff) | |
| download | yosys-06a344efcb4a8c56f230715481ce07e715a7a4b3.tar.gz yosys-06a344efcb4a8c56f230715481ce07e715a7a4b3.tar.bz2 yosys-06a344efcb4a8c56f230715481ce07e715a7a4b3.zip | |
ilang, ast: Store parameter order and default value information.
Fixes #1819, #1820.
Diffstat (limited to 'kernel/rtlil.cc')
| -rw-r--r-- | kernel/rtlil.cc | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 8af941c85..0e9347267 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1389,7 +1389,7 @@ void RTLIL::Module::sort() { wires_.sort(sort_by_id_str()); cells_.sort(sort_by_id_str()); - avail_parameters.sort(sort_by_id_str()); + parameter_default_values.sort(sort_by_id_str()); memories.sort(sort_by_id_str()); processes.sort(sort_by_id_str()); for (auto &it : cells_) @@ -1508,6 +1508,7 @@ void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const log_assert(new_mod->refcount_cells_ == 0); new_mod->avail_parameters = avail_parameters; + new_mod->parameter_default_values = parameter_default_values; for (auto &conn : connections_) new_mod->connect(conn); |