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* Merge remote-tracking branch 'origin/master' into xc7muxEddie Hung2019-05-2112-72/+473
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| * Read bigger Verilog files.Kaj Tuomi2019-05-181-1/+1
| * Merge pull request #1013 from antmicro/parameter_attributesClifford Wolf2019-05-161-2/+2
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| | * Added support for parsing attributes on parameters in Verilog frontent. Conte...Maciej Kurc2019-05-161-2/+2
| * | Make the generated *.tab.hh include all the headers needed to define the union.Henner Zeller2019-05-142-2/+18
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| * Merge pull request #946 from YosysHQ/clifford/specifyClifford Wolf2019-05-068-35/+366
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| | * Add "real" keyword to ilang formatClifford Wolf2019-05-062-1/+8
| | * Merge branch 'master' of github.com:YosysHQ/yosys into clifford/specifyClifford Wolf2019-05-062-2/+10
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| | * | Improve write_verilog specify supportClifford Wolf2019-05-041-0/+3
| | * | Merge remote-tracking branch 'origin/master' into clifford/specifyEddie Hung2019-05-033-2/+14
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| | * | | Improve $specrule interfaceClifford Wolf2019-04-232-9/+19
| | * | | Improve $specrule interfaceClifford Wolf2019-04-231-20/+18
| | * | | Add $specrule cells for $setup/$hold/$skew specify rulesClifford Wolf2019-04-234-4/+86
| | * | | Allow $specify[23] cells in blackbox modulesClifford Wolf2019-04-231-0/+6
| | * | | Rename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better match verilog std nom...Clifford Wolf2019-04-231-2/+2
| | * | | Checking and fixing specify cells in genRTLILClifford Wolf2019-04-231-1/+15
| | * | | Un-break default specify parserClifford Wolf2019-04-231-0/+1
| | * | | Add specify parserClifford Wolf2019-04-234-33/+243
| * | | | Merge pull request #975 from YosysHQ/clifford/fix968Clifford Wolf2019-05-061-2/+0
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| | * \ \ \ Merge branch 'master' of github.com:YosysHQ/yosys into clifford/fix968Clifford Wolf2019-05-065-4/+15
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| | * | | | | Re-enable "final loop assignment" featureClifford Wolf2019-05-011-2/+0
| * | | | | | Merge pull request #871 from YosysHQ/verific_importClifford Wolf2019-05-062-26/+71
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| | * | | | | For hier_tree::Elaborate() also include SV root modules (bind)Eddie Hung2019-05-031-23/+36
| | * | | | | Fix verific_parameters construction, use attribute to mark top netlistsEddie Hung2019-05-032-8/+12
| | * | | | | WIP -chparam support for hierarchy when verificEddie Hung2019-05-032-12/+17
| | * | | | | verific_import() changes to avoid ElaborateAll()Eddie Hung2019-05-031-15/+38
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| * | | | | Fix the other bison warning in ilang_parser.yClifford Wolf2019-05-061-1/+1
| * | | | | verilog_parser: Fix Bison warningBen Widawsky2019-05-051-1/+1
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| * | | | Merge pull request #988 from YosysHQ/clifford/fix987Clifford Wolf2019-05-042-1/+5
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| | * | | | Add approximate support for SV "var" keyword, fixes #987Clifford Wolf2019-05-042-1/+5
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| * / / / Add support for SVA "final" keywordClifford Wolf2019-05-042-1/+5
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| * | | Add splitcmplxassign test case and silence splitcmplxassign warningClifford Wolf2019-05-011-0/+1
| * | | Fix width detection of memory access with bit slice, fixes #974Clifford Wolf2019-05-011-0/+2
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* | | Merge remote-tracking branch 'origin/master' into xc7muxEddie Hung2019-05-022-2/+11
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| * | Disabled "final loop assignment" featureClifford Wolf2019-04-301-0/+2
| * | Merge pull request #972 from YosysHQ/clifford/fix968Clifford Wolf2019-04-301-0/+7
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| | * | Add final loop variable assignment when unrolling for-loops, fixes #968Clifford Wolf2019-04-301-0/+7
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| * / Include filename in "Executing Verilog-2005 frontend" message, fixes #959Clifford Wolf2019-04-301-2/+2
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* | Refactor into AigerReader::post_process()Eddie Hung2019-04-232-249/+161
* | Temporarily remove 'r' extensionEddie Hung2019-04-221-18/+0
* | Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-04-222-7/+38
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| * Merge pull request #952 from YosysHQ/clifford/fix370Clifford Wolf2019-04-221-3/+18
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| | * Determine correct signedness and expression width in for loop unrolling, fixe...Clifford Wolf2019-04-221-3/+18
| * | Add log_debug() frameworkClifford Wolf2019-04-221-2/+0
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| * Merge pull request #909 from zachjs/masterClifford Wolf2019-04-221-1/+20
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| | * support repeat loops with constant repeat counts outside of constant functionsZachary Snow2019-04-091-1/+20
* | | Merge remote-tracking branch 'origin/clifford/libwb' into xaigEddie Hung2019-04-215-35/+111
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| * | Add "noblackbox" attributeClifford Wolf2019-04-211-17/+27
| * | New behavior for front-end handling of whiteboxesClifford Wolf2019-04-205-34/+100
* | | read_aiger to parse 'r' extensionEddie Hung2019-04-181-0/+18
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