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| author | Eddie Hung <eddie@fpgeh.com> | 2019-03-13 22:05:55 +0000 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2019-05-03 20:53:25 +0200 |
| commit | 3ea54ec400bf37f929f168ff5438059c200843c0 (patch) | |
| tree | f7351b12d0c6be554d061d77eeaec53e6ed8cdf1 /frontends | |
| parent | a27b42e97571c817b0698964329d61dddc6e9a3a (diff) | |
| download | yosys-3ea54ec400bf37f929f168ff5438059c200843c0.tar.gz yosys-3ea54ec400bf37f929f168ff5438059c200843c0.tar.bz2 yosys-3ea54ec400bf37f929f168ff5438059c200843c0.zip | |
Fix verific_parameters construction, use attribute to mark top netlists
Diffstat (limited to 'frontends')
| -rw-r--r-- | frontends/verific/verific.cc | 18 | ||||
| -rw-r--r-- | frontends/verific/verific.h | 2 |
2 files changed, 12 insertions, 8 deletions
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 58a29ada4..a05fd29b5 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -775,9 +775,9 @@ void VerificImporter::merge_past_ffs(pool<RTLIL::Cell*> &candidates) merge_past_ffs_clock(it.second, it.first.first, it.first.second); } -void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::set<Netlist*> &nl_todo, bool top) +void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::set<Netlist*> &nl_todo) { - std::string netlist_name = top ? nl->CellBaseName() : nl->Owner()->Name(); + std::string netlist_name = nl->GetAtt(" \\top") ? nl->CellBaseName() : nl->Owner()->Name(); std::string module_name = nl->IsOperator() ? "$verific$" + netlist_name : RTLIL::escape_id(netlist_name); netlist = nl; @@ -1768,7 +1768,7 @@ void verific_import(Design *design, const std::map<std::string,std::string> &par if (veri_lib) veri_libs.InsertLast(veri_lib); Map verific_params(STRING_HASH); - for (auto i : parameters) + for (const auto &i : parameters) verific_params.Insert(i.first.c_str(), i.second.c_str()); if (top.empty()) { @@ -1800,8 +1800,10 @@ void verific_import(Design *design, const std::map<std::string,std::string> &par int i; FOREACH_ARRAY_ITEM(netlists, i, nl) { - if (top.empty() || nl->CellBaseName() == top) - nl_todo.insert(nl); + if (top.empty() && nl->CellBaseName() != top) + continue; + nl->AddAtt(new Att(" \\top", NULL)); + nl_todo.insert(nl); } delete netlists; @@ -1817,7 +1819,7 @@ void verific_import(Design *design, const std::map<std::string,std::string> &par Netlist *nl = *nl_todo.begin(); if (nl_done.count(nl) == 0) { VerificImporter importer(false, false, false, false, false, false); - importer.import_netlist(design, nl, nl_todo, nl->CellBaseName() == top); + importer.import_netlist(design, nl, nl_todo); } nl_todo.erase(nl); nl_done.insert(nl); @@ -2322,8 +2324,10 @@ struct VerificPass : public Pass { Netlist *nl; int i; - FOREACH_ARRAY_ITEM(netlists, i, nl) + FOREACH_ARRAY_ITEM(netlists, i, nl) { + nl->AddAtt(new Att(" \\top", NULL)); nl_todo.insert(nl); + } delete netlists; } diff --git a/frontends/verific/verific.h b/frontends/verific/verific.h index fb44b1736..88a6cc0ba 100644 --- a/frontends/verific/verific.h +++ b/frontends/verific/verific.h @@ -93,7 +93,7 @@ struct VerificImporter void merge_past_ffs_clock(pool<RTLIL::Cell*> &candidates, SigBit clock, bool clock_pol); void merge_past_ffs(pool<RTLIL::Cell*> &candidates); - void import_netlist(RTLIL::Design *design, Verific::Netlist *nl, std::set<Verific::Netlist*> &nl_todo, bool top=false); + void import_netlist(RTLIL::Design *design, Verific::Netlist *nl, std::set<Verific::Netlist*> &nl_todo); }; void verific_import_sva_assert(VerificImporter *importer, Verific::Instance *inst); |