| Commit message (Expand) | Author | Age | Files | Lines |
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| * | Merge pull request #2131 from YosysHQ/claire/preserveffs | clairexen | 2020-06-10 | 1 | -0/+3 |
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| | * | Do not optimize away FFs in "prep" and Verific fron-end | Claire Wolf | 2020-06-09 | 1 | -0/+3 |
| * | | verific - detect missing memory to prevent crash. | Miodrag Milanovic | 2020-06-10 | 1 | -2/+7 |
| * | | Merge pull request #2112 from YosysHQ/claire/fix2040 | clairexen | 2020-06-09 | 2 | -0/+58 |
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| | * | Add latch detection for use_case_method in part-select write, fixes #2040 | Claire Wolf | 2020-06-04 | 2 | -0/+58 |
| * | | Support packed arrays in struct/union. | Peter Crozier | 2020-06-07 | 2 | -17/+136 |
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| * | Merge pull request #2041 from PeterCrozier/struct | clairexen | 2020-06-04 | 6 | -204/+526 |
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| | * | Merge branch 'master' into struct | Peter Crozier | 2020-06-03 | 8 | -53/+95 |
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| | * | | Allow structs within structs. | Peter Crozier | 2020-05-12 | 1 | -7/+18 |
| | * | | Generalise structs and add support for packed unions. | Peter Crozier | 2020-05-12 | 6 | -58/+147 |
| | * | | Implement SV structs. | Peter Crozier | 2020-05-08 | 6 | -205/+427 |
| * | | | Merge pull request #2077 from YosysHQ/eddie/abc9_dff_improve | Eddie Hung | 2020-06-04 | 1 | -2/+5 |
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| | * | | | aiger: cleanup | Eddie Hung | 2020-05-25 | 1 | -2/+5 |
| * | | | | Merge pull request #2006 from jersey99/signed-in-rtlil-wire | whitequark | 2020-06-04 | 3 | -1/+10 |
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| | * | | | frontends/json/jsonparse.cc: Like the upto field read_json can also read the ... | Vamsi K Vytla | 2020-04-27 | 1 | -1/+6 |
| | * | | | Preserve 'signed'-ness of a verilog wire through RTLIL | Vamsi K Vytla | 2020-04-27 | 2 | -0/+4 |
| * | | | | Support asymmetric memories for verific frontend | Miodrag Milanovic | 2020-06-01 | 1 | -6/+1 |
| * | | | | Merge pull request #2029 from whitequark/fix-simplify-memory-sv_logic | clairexen | 2020-05-29 | 1 | -2/+2 |
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| | * | | | | ast/simplify: don't bitblast async ROMs declared as `logic`. | whitequark | 2020-05-05 | 1 | -2/+2 |
| * | | | | | Merge pull request #2097 from whitequark/ilang_lexer-fix-erange | whitequark | 2020-05-29 | 1 | -1/+3 |
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| | * | | | | | ilang_lexer: fix check for out of range literal. | whitequark | 2020-05-29 | 1 | -1/+3 |
| * | | | | | | Merge pull request #2033 from boqwxp/cleanup-verilog-lexer | whitequark | 2020-05-29 | 1 | -6/+5 |
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| | * | | | | | verilog: Move lexer location variables from global namespace to `VERILOG_FRON... | Alberto Gonzalez | 2020-05-06 | 1 | -6/+5 |
| * | | | | | | Silence spurious warning in Verilog lexer when compiling with GCC | Rupert Swarbrick | 2020-05-26 | 1 | -1/+3 |
| * | | | | | | verilog: move attr from simple_behav_stmt to its children to attach | Eddie Hung | 2020-05-25 | 1 | -13/+17 |
| * | | | | | | verilog: do not warn for attributes on null statements | Eddie Hung | 2020-05-25 | 1 | -2/+0 |
| * | | | | | | verilog: handle empty generate statement by removing gen_stmt_or_null... | Eddie Hung | 2020-05-25 | 1 | -7/+8 |
| * | | | | | | verilog: fix #2037 by permitting (and freeing) attributes on null stmt | Eddie Hung | 2020-05-25 | 1 | -1/+5 |
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| * | | | | | Merge pull request #2057 from YosysHQ/eddie/fix_task_attr | Eddie Hung | 2020-05-21 | 1 | -11/+9 |
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| | * | | | | | Update frontends/verilog/verilog_parser.y | Eddie Hung | 2020-05-21 | 1 | -1/+1 |
| | * | | | | | verilog: attributes before task enable (but 13 s/r conflicts) | Eddie Hung | 2020-05-14 | 1 | -10/+8 |
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| * | | | | | Add force_downto and force_upto wire attributes. | Marcelina Kościelnicka | 2020-05-19 | 2 | -1/+20 |
| * | | | | | Merge pull request #1926 from YosysHQ/eddie/abc9_auto_dff | Eddie Hung | 2020-05-18 | 2 | -4/+12 |
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| | * | | | | | aiger: -xaiger to return $_FF_ flops | Eddie Hung | 2020-05-14 | 1 | -15/+2 |
| | * | | | | | aiger/xaiger: use odd for negedge clk, even for posedge | Eddie Hung | 2020-05-14 | 1 | -4/+3 |
| | * | | | | | aiger: -xaiger to parse initial state back into (* init *) on Q wire | Eddie Hung | 2020-05-14 | 1 | -1/+2 |
| | * | | | | | aiger: -xaiger to read $_DFF_[NP]_ back with new clocks created | Eddie Hung | 2020-05-14 | 2 | -3/+24 |
| * | | | | | | Revert "Add support for non-power-of-two mem chunks in verific importer" | Claire Wolf | 2020-05-17 | 1 | -12/+2 |
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| * | | | | | Merge pull request #2045 from YosysHQ/eddie/fix2042 | Eddie Hung | 2020-05-14 | 1 | -1/+13 |
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| | * | | | | | verilog: default to input in sv mode if task/func has no dir ... | Eddie Hung | 2020-05-13 | 1 | -2/+10 |
| | * | | | | | verilog: error out when non-ANSI task/func arguments | Eddie Hung | 2020-05-11 | 1 | -1/+5 |
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| * | | | | | Merge pull request #2052 from YosysHQ/claire/verific_memfix | Claire Wolf | 2020-05-14 | 1 | -2/+12 |
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| | * | | | | | Add support for non-power-of-two mem chunks in verific importer | Claire Wolf | 2020-05-14 | 1 | -2/+12 |
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| * | | | | | Merge pull request #2027 from YosysHQ/eddie/verilog_neg_upto | Claire Wolf | 2020-05-14 | 1 | -1/+1 |
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| | * | | | | ast: swap range regardless of range_left >= 0 | Eddie Hung | 2020-05-04 | 1 | -1/+1 |
| * | | | | | Merge pull request #2022 from Xiretza/fallthroughs | whitequark | 2020-05-08 | 2 | -4/+5 |
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| | * | | | | | Add YS_FALLTHROUGH macro to mark case fall-through | Xiretza | 2020-05-07 | 2 | -4/+5 |
| * | | | | | | Merge pull request #2005 from YosysHQ/claire/fix1990 | Claire Wolf | 2020-05-07 | 5 | -16/+82 |
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| | * | | | | | Fix handling of signed indices in bit slices | Claire Wolf | 2020-05-02 | 1 | -3/+8 |
| | * | | | | | Add AST_SELFSZ and improve handling of bit slices | Claire Wolf | 2020-05-02 | 5 | -7/+22 |
