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| author | Eddie Hung <eddie@fpgeh.com> | 2020-05-25 07:17:54 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-05-25 08:43:33 -0700 |
| commit | 1ebf7155a7d96a529432d93979fb553f12b9d641 (patch) | |
| tree | 124283cf5d86ce947431de6d55d3a6b5e3516f7a /frontends | |
| parent | 9e6c288e5a8b69950f8e4ca394f6acee78f15a18 (diff) | |
| download | yosys-1ebf7155a7d96a529432d93979fb553f12b9d641.tar.gz yosys-1ebf7155a7d96a529432d93979fb553f12b9d641.tar.bz2 yosys-1ebf7155a7d96a529432d93979fb553f12b9d641.zip | |
aiger: cleanup
Diffstat (limited to 'frontends')
| -rw-r--r-- | frontends/aiger/aigerparse.cc | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index d25587e48..fef788267 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -775,7 +775,6 @@ void AigerReader::post_process() } } - dict<int, Wire*> mergeability_to_clock; for (uint32_t i = 0; i < flopNum; i++) { RTLIL::Wire *d = outputs[outputs.size() - flopNum + i]; log_assert(d); @@ -895,7 +894,9 @@ void AigerReader::post_process() } else if (type == "box") { RTLIL::Cell* cell = module->cell(stringf("$box%d", variable)); - if (cell) // ABC could have optimised this box away + if (!cell) + log_debug("Box %d (%s) no longer exists.\n", variable, log_id(escaped_s)); + else module->rename(cell, escaped_s); } else @@ -907,6 +908,8 @@ void AigerReader::post_process() auto name = wp.first; int min = wp.second.first; int max = wp.second.second; + if (min == 0 && max == 0) + continue; RTLIL::Wire *wire = module->wire(name); if (wire) |