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* Fix bison warning for "pure-parser" optionClaire Wolf2020-03-031-1/+1
* Merge pull request #1718 from boqwxp/precise_locationsClaire Wolf2020-03-038-299/+384
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| * Closes #1717. Add more precise Verilog source location information to AST and...Alberto Gonzalez2020-02-238-299/+384
* | Merge pull request #1681 from YosysHQ/eddie/fix1663Claire Wolf2020-03-031-15/+13
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| * | verilog: instead of modifying localparam size, extend init constant exprEddie Hung2020-02-051-15/+13
* | | Merge pull request #1724 from YosysHQ/eddie/abc9_specifyEddie Hung2020-03-022-12/+20
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| * | | ast: quiet down when deriving blackbox modulesEddie Hung2020-02-272-12/+20
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* | | ast: fixes #1710; do not generate RTLIL for unreachable ternaryEddie Hung2020-02-271-9/+22
* | | Comment out log()Eddie Hung2020-02-271-1/+1
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* | Merge pull request #1703 from YosysHQ/eddie/specify_improveEddie Hung2020-02-213-36/+92
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| * | verilog: add support for more delays than just rise/fallEddie Hung2020-02-191-1/+40
| * | verilog: ignore ranges too without -specifyEddie Hung2020-02-131-1/+2
| * | verilog: improve specify support when not in -specify modeEddie Hung2020-02-131-13/+7
| * | verilog: ignore '&&&' when not in -specify modeEddie Hung2020-02-132-5/+6
| * | specify: system timing checks to accept min:typ:max tripleEddie Hung2020-02-131-12/+29
| * | verilog: fix $specify3 checkEddie Hung2020-02-131-7/+11
* | | Merge pull request #1642 from jjj11x/jjj11x/sv-enumClaire Wolf2020-02-205-18/+325
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| * | remove unnecessary blank lineJeff Wang2020-02-171-2/+1
| * | add attributes for enumerated values in ilangJeff Wang2020-02-173-2/+76
| * | separate out enum_item/param implementation when they should be differentJeff Wang2020-02-171-7/+16
| * | fix bug introduced by not taking all of PeterCrozier's changes in 16ea4ea6Jeff Wang2020-01-171-4/+6
| * | fix enum in generate blocksJeff Wang2020-01-161-0/+20
| * | allow enums to be declared at toplevel scopeJeff Wang2020-01-161-0/+7
| * | lexer doesn't seem to return TOK_REG for logic anymoreJeff Wang2020-01-161-3/+4
| * | allow enum typedefsJeff Wang2020-01-161-1/+6
| * | partial rebase of PeterCrozier's enum work onto current masterJeff Wang2020-01-165-17/+207
* | | Merge pull request #1679 from thasti/delay-parsingN. Engelhardt2020-02-131-2/+2
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| * | | correct wire declaration grammar for #1614Stefan Biereigel2020-02-031-2/+2
* | | | Modified $readmem[hb] to use '\' or '/' according the OSRodrigo Alejandro Melo2020-02-061-1/+6
* | | | Merge branch 'master' of https://github.com/YosysHQ/yosysRodrigo Alejandro Melo2020-02-034-94/+118
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| * | | sv: Improve handling of wildcard port connectionsDavid Shah2020-02-022-4/+6
| * | | hierarchy: Resolve SV wildcard port connectionsDavid Shah2020-02-021-1/+1
| * | | sv: Add lexing and parsing of .* (wildcard port conns)David Shah2020-02-022-1/+6
| * | | Merge pull request #1647 from YosysHQ/dave/sprintfDavid Shah2020-02-022-93/+110
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| | * | | ast: Add support for $sformatf system functionDavid Shah2020-01-192-93/+110
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* | | | Replaced strlen by GetSize into simplify.ccRodrigo Alejandro Melo2020-02-031-2/+2
* | | | Fixed a bug in the new feature of $readmem[hb] when an empty string is providedRodrigo Alejandro Melo2020-02-011-1/+1
* | | | Modified the new search for files of $readmem[hb] to be backward compatibleRodrigo Alejandro Melo2020-01-311-3/+7
* | | | $readmem[hb] file inclusion is now relative to the Verilog fileRodrigo Alejandro Melo2020-01-311-1/+2
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* | | Merge pull request #1667 from YosysHQ/clifford/verificnandClaire Wolf2020-01-301-0/+8
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| * | Add Verific support for OPER_REDUCE_NANDClaire Wolf2020-01-301-0/+8
* | | Merge pull request #1503 from YosysHQ/eddie/verific_helpClaire Wolf2020-01-301-8/+8
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| * \ \ Merge remote-tracking branch 'origin/master' into eddie/verific_helpEddie Hung2020-01-2711-229/+347
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| * | | verific: no help() when no YOSYS_ENABLE_VERIFICEddie Hung2020-01-271-4/+1
| * | | OopsEddie Hung2019-11-191-1/+1
| * | | Print help message for verific passEddie Hung2019-11-191-9/+12
* | | | Merge pull request #1654 from YosysHQ/eddie/sby_fix69Claire Wolf2020-01-301-0/+6
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| * | | verific: also unflatten for 'hierarchy' flow as per @cliffordwolfEddie Hung2020-01-271-0/+3
| * | | verific: unflatten struct portsEddie Hung2020-01-241-0/+3
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* | | Add and use SigSpec::reverse()Eddie Hung2020-01-281-3/+3
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