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authorClaire Wolf <clifford@clifford.at>2020-01-30 19:55:53 +0100
committerGitHub <noreply@github.com>2020-01-30 19:55:53 +0100
commit2ce7a0d369ff73b483364e8fbb44c4887f17385f (patch)
treeea984c07f3cd40423ffbc4073482ef0f759c99c0 /frontends
parent60876ce183ee5f3980c378e190d996453d59a780 (diff)
parent23c44afaed7c3fb97b01ca241731fc84dd03d5a7 (diff)
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Merge pull request #1667 from YosysHQ/clifford/verificnand
Add Verific support for OPER_REDUCE_NAND
Diffstat (limited to 'frontends')
-rw-r--r--frontends/verific/verific.cc8
1 files changed, 8 insertions, 0 deletions
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 33f73f2d0..ae5815f8e 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -539,6 +539,14 @@ bool VerificImporter::import_netlist_instance_cells(Instance *inst, RTLIL::IdStr
return true;
}
+ if (inst->Type() == OPER_REDUCE_NAND) {
+ Wire *tmp = module->addWire(NEW_ID);
+ cell = module->addReduceAnd(inst_name, IN, tmp, SIGNED);
+ module->addNot(NEW_ID, tmp, net_map_at(inst->GetOutput()));
+ import_attributes(cell->attributes, inst);
+ return true;
+ }
+
if (inst->Type() == OPER_REDUCE_OR) {
cell = module->addReduceOr(inst_name, IN, net_map_at(inst->GetOutput()), SIGNED);
import_attributes(cell->attributes, inst);