iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
...
\| *	Allow attributes on individual switch cases in RTLIL.	whitequark	2019-07-08	1	-4/+9
\| *	Merge pull request #1147 from YosysHQ/clifford/fix1144	Clifford Wolf	2019-07-03	1	-81/+14
\| \|\
\| \| *	Some cleanups in "ignore specify parser"	Clifford Wolf	2019-07-03	1	-79/+5
\| \| *	Improve specify dummy parser, fixes #1144	Clifford Wolf	2019-06-28	1	-2/+9
\| \| *	Fix segfault on failed VERILOG_FRONTEND::const2ast, closes #1131	Clifford Wolf	2019-06-26	1	-1/+1
* \| \|	Merge remote-tracking branch 'origin/master' into xaig_dff	Eddie Hung	2019-07-02	1	-0/+2
\|\\| \|
\| * \|	Fix read_verilog assert/assume/etc on default case label, fixes YosysHQ/Symbi...	Clifford Wolf	2019-07-02	1	-0/+2
* \| \|	Refactor and cope with new abc_flop format	Eddie Hung	2019-07-01	1	-9/+21
* \| \|	Fix spacing	Eddie Hung	2019-07-01	1	-1/+1
* \| \|	Merge remote-tracking branch 'origin/master' into xaig_dff	Eddie Hung	2019-07-01	9	-77/+189
\|\\| \|
\| * \|	Replace log_assert() with meaningful log_error()	Eddie Hung	2019-06-28	1	-1/+5
\| * \|	Refactor for one "abc_carry" attribute on module	Eddie Hung	2019-06-27	1	-31/+37
\| * \|	Remove unneeded include	Eddie Hung	2019-06-27	1	-3/+0
\| * \|	Merge origin/master	Eddie Hung	2019-06-27	1	-1/+1
\| * \|	Merge remote-tracking branch 'origin/master' into xaig	Eddie Hung	2019-06-24	1	-0/+12
\| \|\\|
\| \| *	Add upto and offset to JSON ports	Miodrag Milanovic	2019-06-21	1	-0/+12
\| * \|	Merge remote-tracking branch 'origin/master' into xaig	Eddie Hung	2019-06-21	3	-6/+19
\| \|\\|
\| \| *	Fix typo	Miodrag Milanovic	2019-06-21	1	-1/+1
\| \| *	Added JSON upto and offset	Clifford Wolf	2019-06-21	1	-0/+12
\| \| *	Merge pull request #1119 from YosysHQ/eddie/fix1118	Clifford Wolf	2019-06-21	1	-0/+1
\| \| \|\
\| \| \| *	Make genvar a signed type	Eddie Hung	2019-06-20	1	-0/+1
\| \| * \|	Maintain "is_unsized" state of constants	Eddie Hung	2019-06-20	1	-6/+6
\| \| \|/
\| * \|	Reduce log_debug spam in parse_xaiger()	Eddie Hung	2019-06-21	1	-16/+19
\| * \|	Workaround issues exposed by gcc-4.8	Eddie Hung	2019-06-21	1	-0/+7
\| * \|	Fix broken abc9.v test due to inout being 1'bx	Eddie Hung	2019-06-20	1	-3/+10
\| * \|	Merge remote-tracking branch 'origin/master' into xaig	Eddie Hung	2019-06-20	6	-15/+77
\| \|\\|
\| \| *	Merge branch 'unpacked_arrays' of https://github.com/towoe/yosys-sv into towo...	Clifford Wolf	2019-06-20	1	-1/+7
\| \| \|\
\| \| \| *	Unpacked array declaration using size	Tobias Wölfel	2019-06-19	1	-1/+7
\| \| * \|	Add "read_verilog -pwires" feature, closes #1106	Clifford Wolf	2019-06-19	5	-9/+44
\| \| * \|	Add defaultvalue attribute	Clifford Wolf	2019-06-19	1	-0/+11
\| \| * \|	Fix handling of "logic" variables with initial value	Clifford Wolf	2019-06-19	1	-2/+2
\| \| * \|	Fixed brojen $error()/$info/$warning() on non-generate blocks	Udi Finkelstein	2019-06-11	2	-3/+13
\| \| \|/
\| * \|	Fix issue with part of PI being 1'bx	Eddie Hung	2019-06-20	1	-4/+6
\| * \|	Cleanup	Eddie Hung	2019-06-16	1	-20/+1
* \| \|	Cleanup	Eddie Hung	2019-06-16	1	-23/+18
* \| \|	Read init from outputs	Eddie Hung	2019-06-15	1	-0/+4
* \| \|	Fix debug message	Eddie Hung	2019-06-15	1	-0/+1
* \| \|	Fix log_debug messages	Eddie Hung	2019-06-15	1	-17/+23
* \| \|	Missing close bracket	Eddie Hung	2019-06-15	1	-1/+1
* \| \|	read_aiger to not require clk_name for latches, plus debug	Eddie Hung	2019-06-15	1	-21/+37
\|/ /
* \|	Cover __APPLE__ too for little to big endian	Eddie Hung	2019-06-14	1	-4/+7
* \|	Further cleanup based on @daveshah1	Eddie Hung	2019-06-14	1	-10/+20
* \|	Resolve comments from @daveshah1	Eddie Hung	2019-06-14	1	-2/+2
* \|	Cleanup	Eddie Hung	2019-06-14	1	-7/+3
* \|	Add TODO to parse_xaiger	Eddie Hung	2019-06-14	1	-0/+1
* \|	Optimise some more	Eddie Hung	2019-06-13	1	-58/+53
* \|	Move ConstEvalAig to aigerparse.cc	Eddie Hung	2019-06-13	1	-3/+161
* \|	Add ConstEvalAig specialised for AIGs	Eddie Hung	2019-06-13	1	-3/+2
* \|	parse_xaiger to cope with inouts	Eddie Hung	2019-06-12	1	-6/+0
* \|	Consistency	Eddie Hung	2019-06-12	2	-2/+2