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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-27 11:20:15 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-27 11:20:15 -0700 |
| commit | 6c256b8cda66e2ba128d5fa3ba344fe4717711f8 (patch) | |
| tree | b8e0a8c4b21139b46f6919abcfcc0bf6ddee0452 /frontends | |
| parent | c226af3f56957cc69b2ce8bb68a8259e26121ddc (diff) | |
| download | yosys-6c256b8cda66e2ba128d5fa3ba344fe4717711f8.tar.gz yosys-6c256b8cda66e2ba128d5fa3ba344fe4717711f8.tar.bz2 yosys-6c256b8cda66e2ba128d5fa3ba344fe4717711f8.zip | |
Merge origin/master
Diffstat (limited to 'frontends')
| -rw-r--r-- | frontends/verilog/const2ast.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/frontends/verilog/const2ast.cc b/frontends/verilog/const2ast.cc index 3a3634d34..f6a17b242 100644 --- a/frontends/verilog/const2ast.cc +++ b/frontends/verilog/const2ast.cc @@ -153,7 +153,7 @@ AstNode *VERILOG_FRONTEND::const2ast(std::string code, char case_type, bool warn { if (warn_z) { AstNode *ret = const2ast(code, case_type); - if (std::find(ret->bits.begin(), ret->bits.end(), RTLIL::State::Sz) != ret->bits.end()) + if (ret != nullptr && std::find(ret->bits.begin(), ret->bits.end(), RTLIL::State::Sz) != ret->bits.end()) log_warning("Yosys has only limited support for tri-state logic at the moment. (%s:%d)\n", current_filename.c_str(), get_line_num()); return ret; |