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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-20 19:27:00 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-20 19:41:27 -0700 |
| commit | 9faeba7a66c34d57bcae6ad83580e640ee5907e6 (patch) | |
| tree | be2e50abcee1b151c7de937d3153e06acd0b9305 /frontends | |
| parent | eb09ea6d54738b82924e33c26f47fe35fbdd24cd (diff) | |
| download | yosys-9faeba7a66c34d57bcae6ad83580e640ee5907e6.tar.gz yosys-9faeba7a66c34d57bcae6ad83580e640ee5907e6.tar.bz2 yosys-9faeba7a66c34d57bcae6ad83580e640ee5907e6.zip | |
Fix broken abc9.v test due to inout being 1'bx
Diffstat (limited to 'frontends')
| -rw-r--r-- | frontends/aiger/aigerparse.cc | 13 |
1 files changed, 10 insertions, 3 deletions
diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index ea3315267..a98ea8314 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -839,6 +839,10 @@ void AigerReader::post_process() RTLIL::Wire* wire = outputs[variable + co_count]; log_assert(wire); log_assert(wire->port_output); + if (escaped_s == "$__dummy__") { + wire->port_output = false; + continue; + } if (index == 0) { // Cope with the fact that a CO might be identical @@ -948,12 +952,15 @@ void AigerReader::post_process() other_wire->port_input = false; other_wire->port_output = false; } - if (wire->port_input && other_wire) - module->connect(other_wire, SigSpec(wire, i)); - else + if (wire->port_input) { + if (other_wire) + module->connect(other_wire, SigSpec(wire, i)); + } + else { // Since we skip POs that are connected to Sx, // re-connect them here module->connect(SigSpec(wire, i), other_wire ? other_wire : SigSpec(RTLIL::Sx)); + } } } |