aboutsummaryrefslogtreecommitdiffstats
path: root/backends
Commit message (Collapse)AuthorAgeFilesLines
...
| * More RTLIL::Cell API usage cleanupsClifford Wolf2014-07-262-35/+35
| |
| * Added RTLIL::Cell::has(portname)Clifford Wolf2014-07-262-3/+3
| |
| * Manual fixes for new cell connections APIClifford Wolf2014-07-262-8/+8
| |
| * Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-267-98/+98
| | | | | | | | | | | | | | | | | | git grep -l 'connections_' | xargs sed -i -r -e ' s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g; s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g; s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g; s/(->|\.)connections_.push_back/\1connect/g; s/(->|\.)connections_/\1connections()/g;'
| * Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-267-98/+98
| |
| * Various RTLIL::SigSpec related code cleanupsClifford Wolf2014-07-253-44/+52
| |
| * Replaced more old SigChunk programming patternsClifford Wolf2014-07-246-40/+28
| |
| * Removed RTLIL::SigSpec::optimize()Clifford Wolf2014-07-234-7/+0
| |
| * Removed RTLIL::SigSpec::expand() methodClifford Wolf2014-07-231-6/+3
| |
| * Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3Clifford Wolf2014-07-232-3/+3
| |
| * Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3Clifford Wolf2014-07-232-3/+3
| |
| * SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, ↵Clifford Wolf2014-07-222-4/+4
| | | | | | | | created interim RTLIL::SigSpec::chunks_rw()
| * SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-228-120/+120
| |
| * SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-228-120/+120
| |
| * Added "autoidx" statement to ilang file formatClifford Wolf2014-07-211-1/+14
| |
| * Use functions instead of always blocks for $mux/$pmux/$safe_pmux in verilog ↵Clifford Wolf2014-07-201-17/+21
| | | | | | | | backend
| * Added support for $bu0 to verilog backendClifford Wolf2014-07-201-0/+16
| |
| * Merged OSX fixes from Siesh1oo with some modificationsClifford Wolf2014-03-131-0/+1
| |
| * Use log_abort() and log_assert() in BTOR backendClifford Wolf2014-03-071-18/+17
| |
| * Added $lut support to blif backend (by user eddiehung from reddit)Clifford Wolf2014-02-221-0/+23
| |
| * Better handling of nameDef and nameRef in edif backendClifford Wolf2014-02-211-21/+27
| |
| * Fixed instantiating multi-bit ports in edif backendClifford Wolf2014-02-211-2/+4
| |
| * Renamed "write_blif -subckt" to "write_blif -icells" and added -gates and -paramClifford Wolf2014-02-211-17/+65
| |
* | fixed memory next issue, when same memory is written in different case statementahmedirfan19832014-09-181-8/+27
| | | | | | | | fixed reduce_xnor, logic_not bug translation bug
* | added $pmux cell translationAhmed Irfan2014-09-021-2/+38
|/
* modified btor synthesis script for correct use of splice command.Ahmed Irfan2014-02-122-6/+6
|
* disabling splice command in the scriptAhmed Irfan2014-02-112-2/+6
|
* register output correctedAhmed Irfan2014-02-111-1/+1
|
* added concat and slice cell translationAhmed Irfan2014-02-113-36/+59
|
* Added $slice and $concat cell typesClifford Wolf2014-02-071-0/+22
|
* Fixed gcc compiler warnings with release buildClifford Wolf2014-02-061-1/+1
|
* Added BTOR backend README fileClifford Wolf2014-02-052-1/+24
|
* Added support for dump -appendClifford Wolf2014-02-041-3/+12
|
* Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)Clifford Wolf2014-02-032-1/+6
|
* Merge branch 'btor' of https://github.com/ahmedirfan1983/yosysClifford Wolf2014-01-261-1/+5
|\
| * root bug correctedAhmed Irfan2014-01-251-1/+5
| |
* | beautified write_intersynthJohann Glaser2014-01-251-0/+9
|/
* removed regex includeAhmed Irfan2014-01-241-1/+0
|
* merged clifford changes + removed regexAhmed Irfan2014-01-241-26/+52
|
* Use techmap -share_map in btor scriptsClifford Wolf2014-01-242-2/+2
|
* Moved btor scripts to backends/btor/Clifford Wolf2014-01-242-0/+50
|
* slice bug correctedAhmed Irfan2014-01-201-1/+1
|
* assert featureAhmed Irfan2014-01-201-9/+40
|
* verilog default options pullAhmed Irfan2014-01-171-28/+97
| | | | shift operator width issues
* slice error correctedAhmed Irfan2014-01-161-5/+5
|
* width issuesAhmed Irfan2014-01-151-64/+87
| | | | dff cell for more than one registers
* BTOR backendAhmed Irfan2014-01-141-274/+328
|
* Merge branch 'master' of https://github.com/cliffordwolf/yosys into btorAhmed Irfan2014-01-032-7/+9
|\
| * Updated manual/command-reference-manual.texClifford Wolf2013-12-281-1/+1
| |
| * Added support for non-const === and !== (for miter circuits)Clifford Wolf2013-12-271-6/+8
| |
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-22 08:44:28 +0000