iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Using std::vector<RTLIL::State> instead of RTLIL::Const for RTLIL::SigChunk::...	Clifford Wolf	2014-09-01	1	-1/+2
*	Changed frontend-api from FILE to std::istream	Clifford Wolf	2014-08-23	1	-4/+4
*	Changed backend-api from FILE to std::ostream	Clifford Wolf	2014-08-23	9	-582/+579
*	Fixed AOI/OAI expr handling in verilog backend	Clifford Wolf	2014-08-16	1	-4/+4
*	Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $...	Clifford Wolf	2014-08-16	1	-4/+40
*	Renamed $lut ports to follow A-Y naming scheme	Clifford Wolf	2014-08-15	1	-2/+2
*	Renamed $_INV_ cell type to $_NOT_	Clifford Wolf	2014-08-15	2	-2/+2
*	Refactoring of CellType class	Clifford Wolf	2014-08-14	1	-10/+28
*	Be more conservative with printing decimal numbers in verilog backend	Clifford Wolf	2014-08-02	1	-2/+3
*	Improved verilog output for ordinary $mux cells	Clifford Wolf	2014-08-02	1	-3/+19
*	No implicit conversion from IdString to anything else	Clifford Wolf	2014-08-02	4	-5/+5
*	More cleanups related to RTLIL::IdString usage	Clifford Wolf	2014-08-02	4	-19/+19
*	Renamed port access function on RTLIL::Cell, added param access functions	Clifford Wolf	2014-07-31	4	-86/+86
*	Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace	Clifford Wolf	2014-07-31	2	-4/+8
*	Renamed "write_autotest" to "test_autotb" and moved to passes/tests/	Clifford Wolf	2014-07-29	2	-338/+0
*	Added $shift and $shiftx cell types (needed for correct part select behavior)	Clifford Wolf	2014-07-29	1	-1/+3
*	Added support for "upto" wires to Verilog front- and back-end	Clifford Wolf	2014-07-28	1	-9/+22
*	Added wire->upto flag for signals such as "wire [0:7] x;"	Clifford Wolf	2014-07-28	1	-0/+2
*	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28	7	-11/+5
*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27	8	-22/+22
*	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27	7	-14/+14
*	Refactoring: Renamed RTLIL::Module::wires to wires_	Clifford Wolf	2014-07-27	8	-14/+14
*	More RTLIL::Cell API usage cleanups	Clifford Wolf	2014-07-26	2	-35/+35
*	Added RTLIL::Cell::has(portname)	Clifford Wolf	2014-07-26	2	-3/+3
*	Manual fixes for new cell connections API	Clifford Wolf	2014-07-26	2	-8/+8
*	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26	7	-98/+98
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26	7	-98/+98
*	Various RTLIL::SigSpec related code cleanups	Clifford Wolf	2014-07-25	3	-44/+52
*	Replaced more old SigChunk programming patterns	Clifford Wolf	2014-07-24	6	-40/+28
*	Removed RTLIL::SigSpec::optimize()	Clifford Wolf	2014-07-23	4	-7/+0
*	Removed RTLIL::SigSpec::expand() method	Clifford Wolf	2014-07-23	1	-6/+3
*	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3	Clifford Wolf	2014-07-23	2	-3/+3
*	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3	Clifford Wolf	2014-07-23	2	-3/+3
*	SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created...	Clifford Wolf	2014-07-22	2	-4/+4
*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22	8	-120/+120
*	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22	8	-120/+120
*	Added "autoidx" statement to ilang file format	Clifford Wolf	2014-07-21	1	-1/+14
*	Use functions instead of always blocks for $mux/$pmux/$safe_pmux in verilog b...	Clifford Wolf	2014-07-20	1	-17/+21
*	Added support for $bu0 to verilog backend	Clifford Wolf	2014-07-20	1	-0/+16
*	Merged OSX fixes from Siesh1oo with some modifications	Clifford Wolf	2014-03-13	1	-0/+1
*	Use log_abort() and log_assert() in BTOR backend	Clifford Wolf	2014-03-07	1	-18/+17
*	Added $lut support to blif backend (by user eddiehung from reddit)	Clifford Wolf	2014-02-22	1	-0/+23
*	Better handling of nameDef and nameRef in edif backend	Clifford Wolf	2014-02-21	1	-21/+27
*	Fixed instantiating multi-bit ports in edif backend	Clifford Wolf	2014-02-21	1	-2/+4
*	Renamed "write_blif -subckt" to "write_blif -icells" and added -gates and -param	Clifford Wolf	2014-02-21	1	-17/+65
*	modified btor synthesis script for correct use of splice command.	Ahmed Irfan	2014-02-12	2	-6/+6
*	disabling splice command in the script	Ahmed Irfan	2014-02-11	2	-2/+6
*	register output corrected	Ahmed Irfan	2014-02-11	1	-1/+1
*	added concat and slice cell translation	Ahmed Irfan	2014-02-11	3	-36/+59
*	Added $slice and $concat cell types	Clifford Wolf	2014-02-07	1	-0/+22