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| * | | | | | chformal: Test -coverprecond and reuse the src attributeJannis Harder2022-06-182-2/+27
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| * | | | | | chformal: Add -coverprecond optionGeorge Rennie2022-06-181-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This inserts $cover cells to cover the enable signal (precondition) for the selected formal cells.
* | | | | | | Merge pull request #3126 from georgerennie/equiv_make_assertionsJannis Harder2023-02-142-27/+97
|\ \ \ \ \ \ \ | | | | | | | | | | | | | | | | equiv_make: Add -make_assert option
| * | | | | | | equiv_make: Add -make_assert optionGeorge Rennie2022-06-242-27/+97
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds a -make_assert flag to equiv_make. When used, the pass generates $eqx and $assert cells to encode equivalence instead of $equiv.
* | | | | | | | gatemate: Update CC_PLL parametersPatrick Urban2023-02-141-0/+3
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* | | | | | | | gatemate: Add CC_USR_RSTN primitivePatrick Urban2023-02-141-0/+6
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* | | | | | | | gatemate: Ensure compatibility of LVDS ports with VHDLPatrick Urban2023-02-141-12/+12
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* | | | | | | | Bump versiongithub-actions[bot]2023-02-141-1/+1
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* | | | | | | | Merge pull request #3669 from jix/fix-xprop-tests-yosys-callJannis Harder2023-02-133-52/+60
|\ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | tests: Fix path of yosys invocation in xprop tests
| * | | | | | | | xprop tests: Make iverilog invocation more portableJannis Harder2023-02-131-3/+3
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| * | | | | | | | xprop: Test fixes and abort on test failureJannis Harder2023-02-132-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use `$finish(0)` to silently exit even when using recent iverlog versions. Run `write_verilog -noexpr` before `write_verilog` as the latter can modify the design. This also enables checking the tests results, as xprop should be in a state where the existing tests pass.
| * | | | | | | | xprop: Smaller subset of tests to run by defaultJannis Harder2023-02-131-44/+53
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| * | | | | | | | verilog_backend: Do not run bwmuxmap even if in expr modeJannis Harder2023-02-131-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While bwmuxmap generates equivalent logic, it doesn't propagate x bits in the same way, which can be relevant when writing verilog.
| * | | | | | | | tests: Fix path of yosys invocation in xprop testsJannis Harder2023-02-101-1/+1
| | |_|_|_|/ / / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For now xprop test failures are still expected and ignored, but without this change, they did not even run unless the yosys build was in path.
* | | | | | | | Bump versiongithub-actions[bot]2023-02-131-1/+1
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* | | | | | | | Resolve package types in interfaces (#3658)Dag Lem2023-02-124-3/+34
| |_|_|_|/ / / |/| | | | | | | | | | | | | | | | | | | | * Resolve package types in interfaces * Added test for resolving of package types in interfaces
* | | | | | | Bump versiongithub-actions[bot]2023-02-111-1/+1
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* | | | | | Merge pull request #3667 from jix/xprop-test-make-fixJannis Harder2023-02-101-1/+1
|\ \ \ \ \ \ | | | | | | | | | | | | | | tests: in xprop tests, use MAKE variable if set
| * | | | | | tests: in xprop tests, use MAKE variable if setJannis Harder2023-02-101-1/+1
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* | | | | | | Bump versiongithub-actions[bot]2023-02-091-1/+1
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* | | | | | | Next dev cycleMiodrag Milanovic2023-02-082-2/+5
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* | | | | | | Release version 0.26Miodrag Milanovic2023-02-082-4/+4
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* | | | | | | Merge pull request #3662 from YosysHQ/micko/wide_case_select_boxJannis Harder2023-02-082-4/+82
|\ \ \ \ \ \ \ | |/ / / / / / |/| | | | | | Add Verific import support for OPER_WIDE_CASE_SELECT_BOX
| * | | | | | For case select values use Sa instead of Sx and SzMiodrag Milanovic2023-02-082-5/+42
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| * | | | | | Add verific import support for OPER_WIDE_CASE_SELECT_BOXMiodrag Milanovic2023-02-061-0/+41
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* | | | | | | Updated changelogMiodrag Milanovic2023-02-082-0/+21
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* | | | | | | Merge pull request #3625 from povik/show_cleanupN. Engelhardt2023-02-061-56/+82
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| * | | | | | | passes: show: s/pos/bitpos/ for readabilityMartin Povišer2023-01-131-4/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Martin Povišer <povik@cutebit.org>
| * | | | | | | passes: show: Reuse string parts in generation of portboxesMartin Povišer2023-01-131-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Martin Povišer <povik@cutebit.org>
| * | | | | | | passes: show: Touch chunk iteration in gen_portboxMartin Povišer2023-01-131-8/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Martin Povišer <povik@cutebit.org>
| * | | | | | | passes: show: Label no_signode flagMartin Povišer2023-01-131-20/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Label the flag and rearrange the control flow a bit. Signed-off-by: Martin Povišer <povik@cutebit.org>
| * | | | | | | passes: show: Simplify wire bit range logicMartin Povišer2023-01-131-8/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Martin Povišer <povik@cutebit.org>
| * | | | | | | passes: show: Factor out 'join_label_pieces'Martin Povišer2023-01-131-20/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In two places, we are joining label pieces by a '|' separator. We go about it by putting the separator behind each entry, then removing the trailing separator in a final fixup pass on the built string. For easier reading, replace those occurrences by a new factored-out 'join_label_pieces' function. Signed-off-by: Martin Povišer <povik@cutebit.org>
| * | | | | | | passes: show: Label signed_suffix flagMartin Povišer2023-01-131-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To make it easier to follow what's going on. Signed-off-by: Martin Povišer <povik@cutebit.org>
| * | | | | | | passes: show: s/idx/dot_idx/ for readabilityMartin Povišer2023-01-131-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Martin Povišer <povik@cutebit.org>
| * | | | | | | passes: show: Fix portbox bit ranges in case of driven signalsMartin Povišer2023-01-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When the 'show' pass generates portboxes to detail the connection of cell ports to wires, it has special handling of signal chunk repetitions, but those repetitions are not accounted for in the displayed bit range in case of cell outputs. Fix that, and so bring it into consistence with the behavior on cell inputs. So, taking for example the following Verilog snippet, module DRIVER (Q); output [7:0] Q; assign Q = 8'b10101010; endmodule module main; wire w; DRIVER driver(.Q({8{w}})); endmodule make the show pass display '7:0 - 8x 0:0' in the driver-to-w portbox instead of '7:7 - 8x 0:0' which it displayed formerly. Signed-off-by: Martin Povišer <povik@cutebit.org>
* | | | | | | | Bump versiongithub-actions[bot]2023-02-051-1/+1
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* | | | | | | | Merge pull request #3659 from whitequark/update-abcCatherine2023-02-041-1/+1
|\ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | Bump ABCREV to fix WASM build
| * | | | | | | | Bump ABCREV to fix WASM build.Catherine2023-02-041-1/+1
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* | | | | | | | Bump versiongithub-actions[bot]2023-02-041-1/+1
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* | | | | | | | backends/firrtl: Ensure `modInstance` is validAki Van Ness2023-02-031-0/+6
| |/ / / / / / |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This should fix #3648 where when calling `emit_elaborated_extmodules` it checks to see if a module is a black-box, however there was no validation that the cell type was actually known, and it just always assumed that we would get a valid instance, causing a segfault.
* | | | | | | Bump versiongithub-actions[bot]2023-02-021-1/+1
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* | | | | | | Merge pull request #3655 from jix/smt2_fix_b_op_widthJannis Harder2023-02-011-1/+4
|\ \ \ \ \ \ \ | | | | | | | | | | | | | | | | smt2: Fix operation width computation for boolean producing cells
| * | | | | | | smt2: Fix operation width computation for boolean producing cellsJannis Harder2023-02-011-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The output width for the boolean value should not influence the operation width. The previous incorrect width extension would still produce correct results, but could produce invalid smt2 output for reduction operators when the output width was larger than the width of the vector to which the reduction was applied. This fixes #3654
* | | | | | | | Bump versiongithub-actions[bot]2023-01-311-1/+1
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* | | | | | | | Merge pull request #3650 from jix/rtlil_roundtrip_z_bitsJannis Harder2023-01-304-1/+22
|\ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | backends/rtlil: Do not shorten a value with z bits to 'x
| * | | | | | | | backends/rtlil: Do not shorten a value with z bits to 'xJannis Harder2023-01-294-1/+22
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* | | | | | | | add option to fsm_detect to ignore self-resettingN. Engelhardt2023-01-301-7/+22
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* | | | | | | | add pmux option to bmuxmap for better fsm detection with verific frontendN. Engelhardt2023-01-302-6/+75
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* | | | | | | Bump versiongithub-actions[bot]2023-01-301-1/+1
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