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| author | Martin Povišer <povik@cutebit.org> | 2023-01-12 19:10:00 +0100 |
|---|---|---|
| committer | Martin Povišer <povik@cutebit.org> | 2023-01-13 19:57:24 +0100 |
| commit | e3709ce7767c0e23568cf89366fc049a47bdc5e1 (patch) | |
| tree | 871b5d3ee2dd109b829158530b98a0ae59a8caaf | |
| parent | 956c4e485a9463863f60c4dd03372db3fa8332a4 (diff) | |
| download | yosys-e3709ce7767c0e23568cf89366fc049a47bdc5e1.tar.gz yosys-e3709ce7767c0e23568cf89366fc049a47bdc5e1.tar.bz2 yosys-e3709ce7767c0e23568cf89366fc049a47bdc5e1.zip | |
passes: show: Fix portbox bit ranges in case of driven signals
When the 'show' pass generates portboxes to detail the connection of
cell ports to wires, it has special handling of signal chunk
repetitions, but those repetitions are not accounted for in the
displayed bit range in case of cell outputs. Fix that, and so bring it
into consistence with the behavior on cell inputs.
So, taking for example the following Verilog snippet,
module DRIVER (Q);
output [7:0] Q;
assign Q = 8'b10101010;
endmodule
module main;
wire w;
DRIVER driver(.Q({8{w}}));
endmodule
make the show pass display '7:0 - 8x 0:0' in the driver-to-w portbox
instead of '7:7 - 8x 0:0' which it displayed formerly.
Signed-off-by: Martin Povišer <povik@cutebit.org>
| -rw-r--r-- | passes/cmds/show.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc index b186e5db2..850bd1889 100644 --- a/passes/cmds/show.cc +++ b/passes/cmds/show.cc @@ -272,7 +272,7 @@ struct ShowWorker std::string repinfo = rep > 1 ? stringf("%dx ", rep) : ""; if (driver) { log_assert(!net.empty()); - label_string += stringf("<s%d> %d:%d - %s%d:%d |", i, pos, pos-c.width+1, repinfo.c_str(), cl, cr); + label_string += stringf("<s%d> %d:%d - %s%d:%d |", i, pos, pos-rep*c.width+1, repinfo.c_str(), cl, cr); net_conn_map[net].in.insert({stringf("x%d:s%d", idx, i), rep*c.width}); net_conn_map[net].color = nextColor(c, net_conn_map[net].color); } else |