diff options
| author | Martin Povišer <povik@cutebit.org> | 2023-01-12 17:24:31 +0100 |
|---|---|---|
| committer | Martin Povišer <povik@cutebit.org> | 2023-01-13 19:57:24 +0100 |
| commit | 8b1f5fba62e2d065d8bc31990927931fb67a4a94 (patch) | |
| tree | 0f856da1e01a58c21ba8a5e39efa98099b8b2705 | |
| parent | ad149cc42aee9394ed5aa2783766fb039d23d2ce (diff) | |
| download | yosys-8b1f5fba62e2d065d8bc31990927931fb67a4a94.tar.gz yosys-8b1f5fba62e2d065d8bc31990927931fb67a4a94.tar.bz2 yosys-8b1f5fba62e2d065d8bc31990927931fb67a4a94.zip | |
passes: show: Simplify wire bit range logic
Signed-off-by: Martin Povišer <povik@cutebit.org>
| -rw-r--r-- | passes/cmds/show.cc | 18 |
1 files changed, 10 insertions, 8 deletions
diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc index c1a0c35ee..5739c79cd 100644 --- a/passes/cmds/show.cc +++ b/passes/cmds/show.cc @@ -261,18 +261,20 @@ struct ShowWorker for (int rep, i = int(sig.chunks().size())-1; i >= 0; i -= rep) { const RTLIL::SigChunk &c = sig.chunks().at(i); int cl, cr; - if (c.wire) { + + cl = c.offset + c.width - 1; + cr = c.offset; + + if (c.is_wire()) { if (c.wire->upto) { - cr = c.wire->start_offset + (c.wire->width - c.offset - 1); + cr = (c.wire->width - 1) - c.offset; cl = cr - (c.width - 1); - } else { - cr = c.wire->start_offset + c.offset; - cl = cr + c.width - 1; } - } else { - cl = c.offset + c.width - 1; - cr = c.offset; + + cl += c.wire->start_offset; + cr += c.wire->start_offset; } + if (!driver && c.wire == nullptr) { RTLIL::State s1 = c.data.front(); for (auto s2 : c.data) |