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| | * | | Fixing issues in CycloneV cell simDiego2019-04-111-3/+9
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| * | | Merge pull request #932 from YosysHQ/eddie/fixdlatchClifford Wolf2019-04-122-3/+4
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* | | | Merge remote-tracking branch 'origin/pmux2shiftx' into xc7muxEddie Hung2019-04-111-1/+0
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| * | | | More unusedEddie Hung2019-04-111-1/+0
* | | | | Merge remote-tracking branch 'origin/pmux2shiftx' into xc7muxEddie Hung2019-04-116-8/+93
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| * | | | Remove unusedEddie Hung2019-04-111-1/+0
| * | | | FixesEddie Hung2019-04-111-20/+16
| * | | | WIPEddie Hung2019-04-112-0/+89
| * | | | Spelling fixesEddie Hung2019-04-111-2/+2
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| * | | Add default entry to testcaseEddie Hung2019-04-111-2/+3
| * | | Recognise default entry in case even if all cases covered (#931)Eddie Hung2019-04-111-1/+1
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| * | Fix a few typosEddie Hung2019-04-081-3/+3
* | | Fix cells_map.v some moreEddie Hung2019-04-111-7/+7
* | | More fine tuningEddie Hung2019-04-111-2/+2
* | | Fix cells_map.vEddie Hung2019-04-111-7/+7
* | | Fix typoEddie Hung2019-04-111-1/+1
* | | Juggle opt calls in synth_xilinxEddie Hung2019-04-112-30/+35
* | | Merge branch 'xaig' into xc7muxEddie Hung2019-04-101-1/+1
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| * | Add non-input bits driven by unrecognised cells as ci_bitsEddie Hung2019-04-101-1/+1
* | | WIP for cells_map.v -- maybe working?Eddie Hung2019-04-101-32/+27
* | | Try splitting $shiftx with Y_WIDTH > 1 into Y_WIDTH = 1Eddie Hung2019-04-101-31/+38
* | | Fix for when B_SIGNED = 1Eddie Hung2019-04-101-1/+8
* | | Update doc for synth_xilinxEddie Hung2019-04-101-7/+8
* | | Merge branch 'xaig' into xc7muxEddie Hung2019-04-101-24/+21
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| * | parse_aiger() to rename all $lut cells after "clean"Eddie Hung2019-04-101-24/+21
* | | ff_map.v after abcEddie Hung2019-04-101-5/+5
* | | Tidy upEddie Hung2019-04-101-1/+1
* | | Move map_cells to before map_lutsEddie Hung2019-04-101-11/+12
* | | WIP for $shiftx to wide muxEddie Hung2019-04-101-1/+63
* | | Update LUT delaysEddie Hung2019-04-101-11/+8
* | | Add cells.lut to techlibs/xilinx/Eddie Hung2019-04-092-0/+16
* | | synth_xilinx to call abc with -lut +/xilinx/cells.lutEddie Hung2019-04-091-2/+2
* | | Add delays to cells.boxEddie Hung2019-04-091-4/+12
* | | Add "-lut <file>" support to abc9Eddie Hung2019-04-091-13/+31
* | | synth_xilinx with abc9 to use -boxEddie Hung2019-04-091-1/+4
* | | Add techlibs/xilinx/cells.boxEddie Hung2019-04-092-0/+6
* | | Add "-box" option to abc9Eddie Hung2019-04-091-7/+22
* | | Add 'setundef -zero' call prior to aigmap in abc9Eddie Hung2019-04-091-0/+4
* | | Comment outEddie Hung2019-04-091-1/+1
* | | Add support for synth_xilinx -abc9 and ignore abc9 -dress optEddie Hung2019-04-092-1/+14
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* | More space fixingEddie Hung2019-04-081-2/+2
* | Fix spacingEddie Hung2019-04-081-29/+29
* | Merge branch 'master' into xaigEddie Hung2019-04-08115-710/+5842
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| * Merge pull request #919 from YosysHQ/multiport_transpClifford Wolf2019-04-081-1/+2
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| | * memory_bram: Fix multiport make_transpDavid Shah2019-04-071-1/+2
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| * Add "read_ilang -lib"Clifford Wolf2019-04-055-3/+39
| * Added missing argument checking to "mutate" commandClifford Wolf2019-04-041-0/+32
| * Merge pull request #913 from smunaut/fix_proc_muxEddie Hung2019-04-031-1/+1
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| | * proc_mux: Fix crash when trying to optimize non-existant mux to shiftxSylvain Munaut2019-04-031-1/+1
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| * Merge pull request #912 from YosysHQ/bram_addr_enClifford Wolf2019-04-031-0/+2
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