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| author | Eddie Hung <eddie@fpgeh.com> | 2019-04-09 10:32:58 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-04-09 10:32:58 -0700 |
| commit | bd523abef5babcc16fbdd67dbf868bd601acaced (patch) | |
| tree | 9941030362618faa3cde147b7cec15655a58654f | |
| parent | 3b6f85b0a6fb08b44dfa7417fce1aeefe9f20e3e (diff) | |
| download | yosys-bd523abef5babcc16fbdd67dbf868bd601acaced.tar.gz yosys-bd523abef5babcc16fbdd67dbf868bd601acaced.tar.bz2 yosys-bd523abef5babcc16fbdd67dbf868bd601acaced.zip | |
Add 'setundef -zero' call prior to aigmap in abc9
| -rw-r--r-- | passes/techmap/abc9.cc | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index ec4a28d08..b0326372e 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -403,6 +403,10 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri RTLIL::Selection& sel = design->selection_stack.back(); sel.select(module); + // Adopt same behaviour as abc + // TODO: How to specify don't-care to abc9? + Pass::call(design, "setundef -zero"); + Pass::call(design, "aigmap"); handle_loops(design); |