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Age
Files
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Add MUXCY and XORCY to cells_box.v
Eddie Hung
2019-04-16
2
-0
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+15
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Fix wire numbering
Eddie Hung
2019-04-16
1
-1
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+2
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Do not put constants into output_bits
Eddie Hung
2019-04-16
1
-2
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+2
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Remove write_verilog call
Eddie Hung
2019-04-16
1
-1
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+1
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Fix spacing
Eddie Hung
2019-04-16
2
-2
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+2
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Merge branch 'xaig' into xc7mux
Eddie Hung
2019-04-16
2
-3
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+1
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Re-enable partsel.v test
Eddie Hung
2019-04-16
1
-1
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+0
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abc9 to call "setundef -zero" behaving as for abc
Eddie Hung
2019-04-16
1
-0
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+3
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NULL check before use
Eddie Hung
2019-04-16
1
-1
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+1
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WIP for box support
Eddie Hung
2019-04-16
1
-36
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+93
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ABC to read_box before reading netlist
Eddie Hung
2019-04-16
1
-1
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+3
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Make cells.box whiteboxes not blackboxes
Eddie Hung
2019-04-16
1
-2
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+2
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read_verilog cells_box.v before techmap
Eddie Hung
2019-04-16
1
-1
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+1
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synth_xilinx: before abc read +/xilinx/cells_box.v
Eddie Hung
2019-04-16
1
-0
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+1
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Add +/xilinx/cells_box.v containing models for ABC boxes
Eddie Hung
2019-04-16
2
-0
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+11
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For 'stat' do not count modules with abc_box_id
Eddie Hung
2019-04-16
1
-0
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+3
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Do not call abc on modules with abc_box_id attr
Eddie Hung
2019-04-16
1
-0
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+3
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Revert "Add abc_box_id attribute to MUXF7/F8 cells"
Eddie Hung
2019-04-16
1
-2
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+0
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Use abc_box_id
Eddie Hung
2019-04-15
1
-2
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+1
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Check abc_box_id attr
Eddie Hung
2019-04-15
1
-1
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+16
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Add abc_box_id attribute to MUXF7/F8 cells
Eddie Hung
2019-04-15
1
-0
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+2
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Merge branch 'xaig' into xc7mux
Eddie Hung
2019-04-15
9
-100
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+246
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Merge remote-tracking branch 'origin/master' into xaig
Eddie Hung
2019-04-15
3
-6
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+5
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Merge pull request #937 from YosysHQ/revert-932-eddie/fixdlatch
Eddie Hung
2019-04-15
2
-4
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+3
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Revert "Recognise default entry in case even if all cases covered (fix for #9...
Eddie Hung
2019-04-15
2
-4
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+3
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Merge pull request #936 from YosysHQ/README-fix-quotes
Eddie Hung
2019-04-15
1
-2
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+2
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README: fix some incorrect quoting.
whitequark
2019-04-15
1
-2
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+2
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Forgot backslashes
Eddie Hung
2019-04-12
1
-1
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+1
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Handle __dummy_o__ and __const[01]__ in read_aiger not abc
Eddie Hung
2019-04-12
2
-18
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+8
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abc to ignore __dummy_o__ and __const[01]__ when re-integrating
Eddie Hung
2019-04-12
1
-6
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+20
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Output __const0__ and __const1__ CIs
Eddie Hung
2019-04-12
1
-7
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+10
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Merge branch 'xaig' of github.com:YosysHQ/yosys into xaig
Eddie Hung
2019-04-12
1
-12
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+32
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Fix inout handling for -map option
Eddie Hung
2019-04-12
1
-10
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+30
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Merge branch 'xaig' of github.com:YosysHQ/yosys into xaig
Eddie Hung
2019-04-12
0
-0
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+0
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Merge remote-tracking branch 'origin/master' into xaig
Eddie Hung
2019-04-12
7
-50
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+76
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Use -map instead of -symbols for aiger
Eddie Hung
2019-04-12
1
-2
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+3
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ci_bits and co_bits now a list, order is important for ABC
Eddie Hung
2019-04-12
1
-24
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+34
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Also cope with duplicated CIs
Eddie Hung
2019-04-12
1
-5
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+23
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WIP
Eddie Hung
2019-04-12
1
-14
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+68
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Comment out
Eddie Hung
2019-04-12
1
-1
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+1
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Add support for synth_xilinx -abc9 and ignore abc9 -dress opt
Eddie Hung
2019-04-12
2
-1
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+14
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Cope with an output having same name as an input (i.e. CO)
Eddie Hung
2019-04-12
1
-5
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+23
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Merge remote-tracking branch 'origin/master' into xaig
Eddie Hung
2019-04-12
7
-50
/
+76
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Merge pull request #928 from litghost/add_xc7_sim_models
Eddie Hung
2019-04-12
3
-41
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+60
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Remove BUFGCTRL, BUFHCE and LUT6_2 from cells_xtra.
Keith Rothman
2019-04-12
3
-52
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+14
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Fix LUT6_2 definition.
Keith Rothman
2019-04-09
1
-3
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+3
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Add additional cells sim models for core 7-series primatives.
Keith Rothman
2019-04-09
1
-0
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+57
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PI before CI
Eddie Hung
2019-04-12
1
-2
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+2
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Merge remote-tracking branch 'origin/master' into xc7mux
Eddie Hung
2019-04-12
1
-3
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+9
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Merge pull request #933 from dh73/master
Clifford Wolf
2019-04-12
1
-3
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+9
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