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| author | Eddie Hung <eddie@fpgeh.com> | 2019-04-08 16:40:17 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-04-08 16:40:17 -0700 |
| commit | 12c34136ba9dfaebe6a33b8e442ed03208c8b217 (patch) | |
| tree | f88c5aa6413614fe5f27b19e59488a5a311fac0f | |
| parent | 36efec01b8b2b29fadc015d5e061a3a21319aea5 (diff) | |
| download | yosys-12c34136ba9dfaebe6a33b8e442ed03208c8b217.tar.gz yosys-12c34136ba9dfaebe6a33b8e442ed03208c8b217.tar.bz2 yosys-12c34136ba9dfaebe6a33b8e442ed03208c8b217.zip | |
More space fixing
| -rw-r--r-- | passes/techmap/abc9.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 3ec365bc0..da3d36354 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -407,7 +407,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri handle_loops(design); - Pass::call(design, stringf("write_xaiger -O -symbols %s/input.aig; ", tempdir_name.c_str())); + Pass::call(design, stringf("write_xaiger -O -symbols %s/input.aig; ", tempdir_name.c_str())); design->selection_stack.pop_back(); @@ -1536,7 +1536,7 @@ struct Abc9Pass : public Pass { } } - Pass::call(design, "clean"); + Pass::call(design, "clean"); assign_map.clear(); signal_map.clear(); |