| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| | * | | | | | Call 'wreduce' after mul2dsp to avoid unextend() | Eddie Hung | 2019-09-25 | 2 | -5/+5 | |
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| | * | | | | | Oops. Actually use __NAME__ in ABC_DSP48E1 macro | Eddie Hung | 2019-09-25 | 1 | -1/+1 | |
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| | * | | | | | Add (* techmap_autopurge *) to abc_unmap.v too | Eddie Hung | 2019-09-23 | 1 | -11/+11 | |
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| | * | | | | | "abc_padding" attr for blackbox outputs that were padded, remove them later | Eddie Hung | 2019-09-23 | 2 | -4/+22 | |
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| | * | | | | | Force $inout.out ports to begin with '$' to indicate internal | Eddie Hung | 2019-09-23 | 2 | -3/+3 | |
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| | * | | | | | Add techmap_autopurge to outputs in abc_map.v too | Eddie Hung | 2019-09-23 | 1 | -11/+11 | |
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| | * | | | | | Revert "Add a xilinx_finalise pass" | Eddie Hung | 2019-09-23 | 3 | -87/+0 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 23d90e0439ffef510632ce45a3d2aff1c129f405. | |||||
| | * | | | | | Revert "Remove (* techmap_autopurge *) from abc_unmap.v since no effect" | Eddie Hung | 2019-09-23 | 1 | -38/+38 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 67c2db3486a7b2ff34f89dc861fb66d51ba6101b. | |||||
| | * | | | | | Revert "Vivado does not like zero width port connections" | Eddie Hung | 2019-09-23 | 1 | -2/+2 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 895e2befa76bd326cc47fd40de112ea067fcaf98. | |||||
| | * | | | | | Vivado does not like zero width port connections | Eddie Hung | 2019-09-23 | 1 | -2/+2 | |
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| | * | | | | | Remove (* techmap_autopurge *) from abc_unmap.v since no effect | Eddie Hung | 2019-09-23 | 1 | -38/+38 | |
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| | * | | | | | Add a xilinx_finalise pass | Eddie Hung | 2019-09-23 | 3 | -0/+87 | |
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| | * | | | | | Set [AB]CASCREG to legal values | Eddie Hung | 2019-09-23 | 1 | -6/+10 | |
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| | * | | | | | Comment to explain separating CREG packing | Eddie Hung | 2019-09-23 | 1 | -0/+8 | |
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| | * | | | | | Separate out CREG packing into new pattern, to avoid conflict with PREG | Eddie Hung | 2019-09-23 | 4 | -46/+273 | |
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| | * | | | | | Move log_debug("\n") later | Eddie Hung | 2019-09-23 | 1 | -1/+1 | |
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| | * | | | | | Move unextend initialisation later | Eddie Hung | 2019-09-23 | 1 | -12/+9 | |
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| | * | | | | | Use new port() overload once more | Eddie Hung | 2019-09-23 | 1 | -2/+2 | |
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| | * | | | | | Merge remote-tracking branch 'origin/master' into xc7dsp | Eddie Hung | 2019-09-23 | 2 | -1/+69 | |
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| | * | | | | | Grammar | Eddie Hung | 2019-09-20 | 1 | -1/+1 | |
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| | * | | | | | Use new port/param overload in pmg | Eddie Hung | 2019-09-20 | 4 | -22/+22 | |
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| | * | | | | | Output pattern matcher items as log_debug() | Eddie Hung | 2019-09-20 | 2 | -31/+27 | |
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| | * | | | | | OPMODE is port not param | Eddie Hung | 2019-09-20 | 1 | -7/+6 | |
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| | * | | | | | Merge remote-tracking branch 'origin/master' into xc7dsp | Eddie Hung | 2019-09-20 | 4 | -18/+50 | |
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| | * | | | | | | Do not run xilinx_dsp_cascadeAB for now | Eddie Hung | 2019-09-20 | 1 | -1/+2 | |
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| | * | | | | | | WIP for xiinx_dsp_cascadeAB | Eddie Hung | 2019-09-20 | 1 | -3/+499 | |
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| | * | | | | | | Run until convergence | Eddie Hung | 2019-09-20 | 1 | -3/+9 | |
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| | * | | | | | | Cleanup ice40_dsp.pmg | Eddie Hung | 2019-09-20 | 1 | -12/+6 | |
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| | * | | | | | | Cleanup xilinx_dsp | Eddie Hung | 2019-09-20 | 1 | -1/+1 | |
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| | * | | | | | | More exceptions | Eddie Hung | 2019-09-20 | 1 | -2/+2 | |
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| | * | | | | | | Fix signedness bug | Eddie Hung | 2019-09-20 | 1 | -2/+2 | |
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| | * | | | | | | Update doc | Eddie Hung | 2019-09-20 | 1 | -2/+2 | |
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| | * | | | | | | Add a xilinx_dsp_cascade matcher for PCIN -> PCOUT | Eddie Hung | 2019-09-20 | 4 | -54/+105 | |
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| | * | | | | | | Add an overload for port/param with default value | Eddie Hung | 2019-09-20 | 1 | -0/+8 | |
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| | * | | | | | | Re-add DSP_A_MINWIDTH, remove unnec. opt_expr -fine from synth_ice40 | Eddie Hung | 2019-09-20 | 2 | -3/+2 | |
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| | * | | | | | | Revert "Move mul2dsp before wreduce" | Eddie Hung | 2019-09-20 | 1 | -4/+5 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit e4f4f6a9d5cf8bb23870fc483f16f66c80ceebab. | |||||
| | * | | | | | | Move mul2dsp before wreduce | Eddie Hung | 2019-09-20 | 1 | -5/+4 | |
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| | * | | | | | | Small cleanup | Eddie Hung | 2019-09-20 | 1 | -19/+18 | |
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| | * | | | | | | Disable support for SB_MAC16 reset since it is async | Eddie Hung | 2019-09-19 | 2 | -3/+7 | |
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| | * | | | | | | SB_MAC16 ffCD to not pack same as ffO | Eddie Hung | 2019-09-19 | 1 | -2/+2 | |
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| | * | | | | | | Add more complicated macc testcase | Eddie Hung | 2019-09-19 | 2 | -5/+39 | |
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| | * | | | | | | Clarify | Eddie Hung | 2019-09-19 | 1 | -1/+2 | |
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| | * | | | | | | Update doc for ice40_dsp | Eddie Hung | 2019-09-19 | 1 | -1/+10 | |
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| | * | | | | | | Tidy up, fix undriven | Eddie Hung | 2019-09-19 | 1 | -32/+34 | |
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| | * | | | | | | Add an index | Eddie Hung | 2019-09-19 | 2 | -0/+3 | |
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| | * | | | | | | $__ABC_REG to have WIDTH parameter | Eddie Hung | 2019-09-19 | 2 | -17/+18 | |
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| | * | | | | | | Fix DSP48E1 timing by breaking P path if MREG or PREG | Eddie Hung | 2019-09-19 | 4 | -349/+363 | |
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| | * | | | | | | Revert "Different approach to timing" | Eddie Hung | 2019-09-19 | 4 | -195/+405 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 41256f48a5f3231e231cbdf9380a26128f272044. | |||||
| | * | | | | | | Different approach to timing | Eddie Hung | 2019-09-19 | 4 | -405/+195 | |
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| | * | | | | | | Fix width of D | Eddie Hung | 2019-09-19 | 1 | -1/+1 | |
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index : iCE40/yosys | |
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