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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-19 21:58:34 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-19 21:58:34 -0700 |
| commit | 1b88211ec61d70ee34f9dc21647ebd941d91fcb4 (patch) | |
| tree | bc4d52faab874645b46fb3da47d1233ac88e1cee | |
| parent | 34f9a8ceb285b6b59f24f994d3a877d5f4f09572 (diff) | |
| download | yosys-1b88211ec61d70ee34f9dc21647ebd941d91fcb4.tar.gz yosys-1b88211ec61d70ee34f9dc21647ebd941d91fcb4.tar.bz2 yosys-1b88211ec61d70ee34f9dc21647ebd941d91fcb4.zip | |
Clarify
| -rw-r--r-- | passes/pmgen/xilinx_dsp.cc | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/passes/pmgen/xilinx_dsp.cc b/passes/pmgen/xilinx_dsp.cc index adc09a6e4..abd145723 100644 --- a/passes/pmgen/xilinx_dsp.cc +++ b/passes/pmgen/xilinx_dsp.cc @@ -507,7 +507,8 @@ struct XilinxDspPass : public Pass { log("\n"); log("Multiply-accumulate operations using the post-adder with feedback on the 'C'\n"); log("input will be folded into the DSP. In this scenario only, the 'C' input can be\n"); - log("used to override the existing accumulation result with a new value.\n"); + log("used to override the current accumulation result with a new value, which will\n"); + log("be added to the multiplier result to form the next accumulation result.\n"); log("\n"); log("Use of the dedicated 'PCOUT' -> 'PCIN' cascade path is detected for 'P' -> 'C'\n"); log("connections (optionally, where 'P' is right-shifted by 18-bits and used as an\n"); |