| Commit message (Expand) | Author | Age | Files | Lines | ||
|---|---|---|---|---|---|---|
| ... | ||||||
| * | | | | | | | | Restore old ffY behaviour | Eddie Hung | 2019-07-19 | 1 | -16/+5 | |
| * | | | | | | | | Cleanup | Eddie Hung | 2019-07-19 | 1 | -5/+5 | |
| * | | | | | | | | Indirection via $__soft_mul | Eddie Hung | 2019-07-19 | 2 | -9/+10 | |
| * | | | | | | | | Do not do sign extension in techmap; let packer do it | Eddie Hung | 2019-07-19 | 1 | -14/+5 | |
| * | | | | | | | | Merge remote-tracking branch 'origin/eddie/wreduce_add' into ice40dsp | Eddie Hung | 2019-07-19 | 3 | -5/+29 | |
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| | * | | | | | | | Add another test | Eddie Hung | 2019-07-19 | 1 | -1/+24 | |
| | * | | | | | | | Do not access beyond bounds | Eddie Hung | 2019-07-19 | 1 | -1/+1 | |
| | * | | | | | | | Add an SigSpec::at(offset, defval) convenience method | Eddie Hung | 2019-07-19 | 1 | -0/+1 | |
| | * | | | | | | | Wrap A and B in sigmap | Eddie Hung | 2019-07-19 | 1 | -2/+2 | |
| | * | | | | | | | Remove "top" from message | Eddie Hung | 2019-07-19 | 1 | -1/+1 | |
| * | | | | | | | | Merge remote-tracking branch 'origin/eddie/wreduce_add' into ice40dsp | Eddie Hung | 2019-07-19 | 2 | -3/+121 | |
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| | * | | | | | | | Also optimise MSB of $sub | Eddie Hung | 2019-07-19 | 1 | -3/+3 | |
| | * | | | | | | | Add one more test with trimming Y_WIDTH of $sub | Eddie Hung | 2019-07-19 | 1 | -11/+14 | |
| | * | | | | | | | Be more explicit | Eddie Hung | 2019-07-19 | 1 | -6/+29 | |
| | * | | | | | | | wreduce for $sub | Eddie Hung | 2019-07-19 | 1 | -0/+23 | |
| | * | | | | | | | Add tests for sub too | Eddie Hung | 2019-07-19 | 1 | -1/+48 | |
| | * | | | | | | | Add test | Eddie Hung | 2019-07-19 | 1 | -0/+22 | |
| | * | | | | | | | SigSpec::extract to take negative lengths | Eddie Hung | 2019-07-19 | 1 | -1/+1 | |
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| * | | | | | | | Do not $mul -> $__mul if A and B are less than maxwidth | Eddie Hung | 2019-07-19 | 1 | -1/+3 | |
| * | | | | | | | Add DSP_MINWIDTH=11 for ice40 since ice40_dsp uses this threshold | Eddie Hung | 2019-07-19 | 1 | -1/+1 | |
| * | | | | | | | Add a DSP_MINWIDTH macro, and soft-logic for {A_WIDTH,B_WIDTH} <= 1 too | Eddie Hung | 2019-07-19 | 1 | -28/+68 | |
| * | | | | | | | Fine tune ice40_dsp.pmg, add support for packing subsets of registers | Eddie Hung | 2019-07-19 | 4 | -35/+47 | |
| * | | | | | | | Add support for ice40 signed multipliers | Eddie Hung | 2019-07-19 | 1 | -13/+8 | |
| * | | | | | | | Merge branch 'xc7dsp' into ice40dsp | Eddie Hung | 2019-07-19 | 1 | -1/+1 | |
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| | * | | | | | | | Fix typo in B | Eddie Hung | 2019-07-19 | 1 | -1/+1 | |
| | * | | | | | | | Merge remote-tracking branch 'origin/master' into xc7dsp | Eddie Hung | 2019-07-18 | 29 | -228/+405 | |
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| * | | | | | | | | Merge remote-tracking branch 'origin/eddie/signed_ice40_dsp' into ice40dsp | Eddie Hung | 2019-07-19 | 3 | -7/+239 | |
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| | * | | | | | | | ice40: Fix test_dsp_model.sh | David Shah | 2019-07-19 | 1 | -1/+1 | |
| | * | | | | | | | ice40/cells_sim.v: Fix sign of J and K partial products | David Shah | 2019-07-19 | 1 | -5/+7 | |
| | * | | | | | | | ice40/cells_sim.v: LSB of A/B only signed in 8x8 mode | David Shah | 2019-07-19 | 1 | -2/+2 | |
| | * | | | | | | | Add tests for all combinations of A and B signedness for comb mul | Eddie Hung | 2019-07-19 | 2 | -1/+229 | |
| | * | | | | | | | Don't copy ref if exists already | Eddie Hung | 2019-07-19 | 1 | -1/+3 | |
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| * | | | | | | | Use sign_headroom instead | Eddie Hung | 2019-07-19 | 1 | -4/+4 | |
| * | | | | | | | Fix SB_MAC sim model -- do not sign extend internal products? | Eddie Hung | 2019-07-18 | 1 | -2/+2 | |
| * | | | | | | | Add params | Eddie Hung | 2019-07-18 | 1 | -0/+6 | |
| * | | | | | | | Merge remote-tracking branch 'origin/master' into ice40dsp | Eddie Hung | 2019-07-18 | 1 | -33/+18 | |
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| | * | | | | | | Merge pull request #1208 from ZirconiumX/intel_cleanups | David Shah | 2019-07-18 | 1 | -29/+14 | |
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| | | * | | | | | | synth_intel: Use stringf | Dan Ravensloft | 2019-07-18 | 1 | -7/+2 | |
| | | * | | | | | | synth_intel: s/not family/no family/ | Dan Ravensloft | 2019-07-18 | 1 | -2/+2 | |
| | | * | | | | | | synth_intel: revert change to run_max10 | Dan Ravensloft | 2019-07-18 | 1 | -1/+1 | |
| | | * | | | | | | intel_synth: Fix help message | Ben Widawsky | 2019-07-18 | 1 | -1/+1 | |
| | | * | | | | | | intel_synth: Small code cleanup to remove if ladder | Ben Widawsky | 2019-07-18 | 2 | -29/+11 | |
| | | * | | | | | | intel_synth: Make family explicit and match | Ben Widawsky | 2019-07-18 | 1 | -2/+6 | |
| | | * | | | | | | intel_synth: Minor code cleanups | Ben Widawsky | 2019-07-18 | 1 | -2/+6 | |
| | * | | | | | | | Merge pull request #1207 from ZirconiumX/intel_new_pass_names | David Shah | 2019-07-18 | 1 | -4/+4 | |
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| | | * | | | | | | synth_intel: rename for consistency with #1184 | Dan Ravensloft | 2019-07-18 | 1 | -4/+4 | |
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| * | | | | | | | Do not define `DSP_SIGNEDONLY macro if no exists | Eddie Hung | 2019-07-18 | 1 | -4/+3 | |
| * | | | | | | | Merge remote-tracking branch 'origin/master' into ice40dsp | Eddie Hung | 2019-07-18 | 28 | -195/+387 | |
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| | * | | | | | | Merge pull request #1184 from whitequark/synth-better-labels | Clifford Wolf | 2019-07-18 | 5 | -17/+21 | |
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| | | * | | | | | | synth_ecp5: rename dram to lutram everywhere. | whitequark | 2019-07-16 | 4 | -13/+13 | |
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index : iCE40/yosys | |
| clone of https://github.com/YosysHQ/yosys |
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