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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-19 20:25:28 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-19 20:25:28 -0700 |
| commit | f9d08a5e5e0ce637b510f6c19a4cd72edf17b3f7 (patch) | |
| tree | e95299ac8172e47d7a8f22b403bc58f498b9c911 | |
| parent | 47fd042b9f8a92df1e1d59042068e7846c4ce808 (diff) | |
| download | yosys-f9d08a5e5e0ce637b510f6c19a4cd72edf17b3f7.tar.gz yosys-f9d08a5e5e0ce637b510f6c19a4cd72edf17b3f7.tar.bz2 yosys-f9d08a5e5e0ce637b510f6c19a4cd72edf17b3f7.zip | |
Cleanup
| -rw-r--r-- | passes/pmgen/ice40_dsp.pmg | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/passes/pmgen/ice40_dsp.pmg b/passes/pmgen/ice40_dsp.pmg index 471b8b519..fb5fe0951 100644 --- a/passes/pmgen/ice40_dsp.pmg +++ b/passes/pmgen/ice40_dsp.pmg @@ -23,10 +23,10 @@ code sigA clock clock_pol sigA = port(mul, \A); if (ffA) { - sigA.replace(port(ffA, \Q), port(ffA, \D)); - clock = port(ffA, \CLK).as_bit(); clock_pol = param(ffA, \CLK_POLARITY).as_bool(); + + sigA.replace(port(ffA, \Q), port(ffA, \D)); } endcode @@ -41,8 +41,6 @@ code sigB clock clock_pol sigB = port(mul, \B); if (ffB) { - sigB.replace(port(ffB, \Q), port(ffB, \D)); - SigBit c = port(ffB, \CLK).as_bit(); bool cp = param(ffB, \CLK_POLARITY).as_bool(); @@ -51,6 +49,8 @@ code sigB clock clock_pol clock = c; clock_pol = cp; + + sigB.replace(port(ffB, \Q), port(ffB, \D)); } endcode @@ -62,7 +62,7 @@ code sigY sigYused for (i = GetSize(sigY); i > 0; i--) if (nusers(sigY[i-1]) > 1) break; - sigYused = sigY.extract(0, i).remove_const(); + sigYused = sigY.extract(0, i); endcode match ffY |