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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-19 13:11:30 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-19 13:11:30 -0700 |
| commit | 5bd088a686ce040c39a8353cf3a7cfe31581d635 (patch) | |
| tree | 0b4d7d160e95dc501a4e42cc6a02df5fe48749ba | |
| parent | 415a2716df8c41193650804158281ef73e7fc655 (diff) | |
| download | yosys-5bd088a686ce040c39a8353cf3a7cfe31581d635.tar.gz yosys-5bd088a686ce040c39a8353cf3a7cfe31581d635.tar.bz2 yosys-5bd088a686ce040c39a8353cf3a7cfe31581d635.zip | |
Add one more test with trimming Y_WIDTH of $sub
| -rw-r--r-- | tests/various/wreduce.ys | 25 |
1 files changed, 14 insertions, 11 deletions
diff --git a/tests/various/wreduce.ys b/tests/various/wreduce.ys index f9e5ed4e3..8030c005e 100644 --- a/tests/various/wreduce.ys +++ b/tests/various/wreduce.ys @@ -9,7 +9,7 @@ hierarchy -auto-top proc design -save gold -prep +prep # calls wreduce select -assert-count 1 t:$add r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i @@ -21,8 +21,8 @@ design -import gate -as gate miter -equiv -flatten -make_assert -make_outputs gold gate miter sat -verify -prove-asserts -show-ports miter +########## -### X - 0 read_verilog <<EOT module wreduce_sub_test1(input [3:0] i, input [7:0] j, output [8:0] o); assign o = j - (i << 4); @@ -33,7 +33,7 @@ hierarchy -auto-top proc design -save gold -prep +prep # calls wreduce select -assert-count 1 t:$sub r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i @@ -45,9 +45,10 @@ design -import gate -as gate miter -equiv -flatten -make_assert -make_outputs gold gate miter sat -verify -prove-asserts -show-ports miter -### 0 - X +########## + read_verilog <<EOT -module wreduce_sub_test1(input [3:0] i, input [7:0] j, output [8:0] o); +module wreduce_sub_test2(input [3:0] i, input [7:0] j, output [8:0] o); assign o = (i << 4) - j; endmodule EOT @@ -56,7 +57,7 @@ hierarchy -auto-top proc design -save gold -prep +prep # calls wreduce select -assert-count 1 t:$sub r:A_WIDTH=8 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i @@ -68,10 +69,11 @@ design -import gate -as gate miter -equiv -flatten -make_assert -make_outputs gold gate miter sat -verify -prove-asserts -show-ports miter -### 0 - X +########## + read_verilog <<EOT -module wreduce_sub_test1(input [3:0] i, input [7:0] j, output [8:0] o); - assign o = (i << 4) - j; +module wreduce_sub_test3(input [3:0] i, input [7:0] j, output [8:0] o); + assign o = (j >> 4) - i; endmodule EOT @@ -79,9 +81,10 @@ hierarchy -auto-top proc design -save gold -prep +prep # calls wreduce -select -assert-count 1 t:$sub r:A_WIDTH=8 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i +dump +select -assert-count 1 t:$sub r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i design -stash gate |