iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Keep track of bits in variable length chain, to check for taps	Eddie Hung	2019-08-23	1	-0/+12
*	Don't forget $dff has no EN	Eddie Hung	2019-08-23	1	-2/+4
*	Same for variable length	Eddie Hung	2019-08-23	1	-2/+10
*	Filter on en_port for fixed length	Eddie Hung	2019-08-23	1	-4/+24
*	Check clock is consistent	Eddie Hung	2019-08-23	1	-5/+25
*	Fix last_cell.D	Eddie Hung	2019-08-23	1	-2/+1
*	Revert "Add a unique argument to pmgen's nusers()"	Eddie Hung	2019-08-23	1	-8/+4
*	Revert "Fix polarity"	Eddie Hung	2019-08-23	1	-1/+1
*	Fix polarity	Eddie Hung	2019-08-23	1	-1/+1
*	Check for non unique nusers/fanouts	Eddie Hung	2019-08-23	1	-2/+2
*	Add a unique argument to pmgen's nusers()	Eddie Hung	2019-08-23	1	-4/+8
*	Update doc	Eddie Hung	2019-08-23	1	-12/+19
*	Remove (* init *) entry when consumed into SRL	Eddie Hung	2019-08-23	1	-2/+6
*	indo -> into	Eddie Hung	2019-08-23	1	-1/+1
*	Forgot to slice	Eddie Hung	2019-08-23	1	-1/+2
*	Cope with possibility that D could connect to Q on same cell	Eddie Hung	2019-08-23	1	-1/+1
*	Mention shregmap -tech xilinx is superseded	Eddie Hung	2019-08-23	1	-1/+1
*	xilinx_srl now copes with word-level flops $dff{,e}	Eddie Hung	2019-08-23	1	-8/+3
*	xilinx_srl to use 'slice' features of pmgen for word level	Eddie Hung	2019-08-23	2	-32/+49
*	Merge remote-tracking branch 'origin/clifford/pmgen' into eddie/xilinx_srl	Eddie Hung	2019-08-23	5	-34/+280
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\| *	Fix port hanlding in pmgen	Clifford Wolf	2019-08-23	1	-4/+3
\| *	Add pmgen slices and choices	Clifford Wolf	2019-08-23	5	-28/+277
* \|	Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl	Eddie Hung	2019-08-23	9	-20/+43
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\| * \|	Forgot one	Eddie Hung	2019-08-23	1	-1/+2
\| * \|	Put abc_* attributes above port	Eddie Hung	2019-08-23	3	-14/+28
\| * \|	Merge pull request #1326 from mmicko/doc-update	Eddie Hung	2019-08-23	1	-2/+5
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\| \| *	Make macOS depenency clear	Miodrag Milanovic	2019-08-23	1	-2/+5
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\| *	Do not propagate mem2reg attribute through to result	Eddie Hung	2019-08-22	2	-1/+3
\| *	Spelling	Eddie Hung	2019-08-22	1	-2/+2
\| *	Merge pull request #1322 from mmicko/pyosys_osx	Eddie Hung	2019-08-22	1	-0/+2
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\| \| *	do not require boost if pyosys is not used	Miodrag Milanovic	2019-08-22	1	-0/+2
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\| *	Merge pull request #1319 from TeaEngineering/shuckc/brew-tcl-tk	Eddie Hung	2019-08-22	1	-0/+1
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\| \| *	require tcl-tk in Brewfile	Chris Shucksmith	2019-08-22	1	-0/+1
* \| \|	In sat: 'x' in init attr should not override constant	Eddie Hung	2019-08-22	3	-1/+7
* \| \|	Remove Xilinx test	Eddie Hung	2019-08-22	1	-34/+0
* \| \|	Actually, there might not be any harm in updating sigmap...	Eddie Hung	2019-08-22	1	-3/+1
* \| \|	Add comment as per @cliffordwolf	Eddie Hung	2019-08-22	1	-0/+11
* \| \|	Add shregmap -tech xilinx test	Eddie Hung	2019-08-22	1	-0/+1
* \| \|	Revert "Try way that doesn't involve creating a new wire"	Eddie Hung	2019-08-22	1	-15/+10
* \| \|	Try way that doesn't involve creating a new wire	Eddie Hung	2019-08-22	1	-10/+15
* \| \|	If d_bit already in sigbit_chain_next, create extra wire	Eddie Hung	2019-08-22	1	-3/+6
* \| \|	Add doc	Eddie Hung	2019-08-22	1	-1/+14
* \| \|	Add copyright	Eddie Hung	2019-08-22	1	-0/+1
* \| \|	Add CHANGELOG entry	Eddie Hung	2019-08-22	1	-0/+2
* \| \|	Remove `shregmap -tech xilinx` additions	Eddie Hung	2019-08-22	1	-189/+8
* \| \|	pmgen to also iterate over all module ports	Eddie Hung	2019-08-22	1	-2/+4
* \| \|	Remove output_bits	Eddie Hung	2019-08-22	2	-16/+7
* \| \|	Forgot to set ud_variable.minlen	Eddie Hung	2019-08-22	1	-0/+1
* \| \|	Do not run xilinx_srl_pm in fixed loop	Eddie Hung	2019-08-22	1	-28/+24
* \| \|	Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl	Eddie Hung	2019-08-22	19	-102/+1046
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