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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-23 13:56:01 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-23 13:56:01 -0700 |
| commit | 3d7f4aa0c8841739eb30fa667181475ce22b4187 (patch) | |
| tree | 1eaf97fe338184cb9b6c44bc039daf900a6b5acd | |
| parent | a1f78eab0466ca328b39750b7746deb336c5c973 (diff) | |
| download | yosys-3d7f4aa0c8841739eb30fa667181475ce22b4187.tar.gz yosys-3d7f4aa0c8841739eb30fa667181475ce22b4187.tar.bz2 yosys-3d7f4aa0c8841739eb30fa667181475ce22b4187.zip | |
Remove (* init *) entry when consumed into SRL
| -rw-r--r-- | passes/pmgen/xilinx_srl.cc | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/passes/pmgen/xilinx_srl.cc b/passes/pmgen/xilinx_srl.cc index e21a826df..d446bf47a 100644 --- a/passes/pmgen/xilinx_srl.cc +++ b/passes/pmgen/xilinx_srl.cc @@ -52,7 +52,9 @@ void run_fixed(xilinx_srl_pm &pm) log_assert(Q.wire); auto it = Q.wire->attributes.find(ID(init)); if (it != Q.wire->attributes.end()) { - initval.append(it->second[Q.offset]); + auto &i = it->second[Q.offset]; + initval.append(i); + i = State::Sx; } else initval.append(State::Sx); @@ -118,7 +120,9 @@ void run_variable(xilinx_srl_pm &pm) log_assert(Q.wire); auto it = Q.wire->attributes.find(ID(init)); if (it != Q.wire->attributes.end()) { - initval.append(it->second[Q.offset]); + auto &i = it->second[Q.offset]; + initval.append(i); + i = State::Sx; } else initval.append(State::Sx); |